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docs/hw/common/board_installation/adp_board_installation/adp_board_installation_guidelines.md

@@ -1,6 +1,6 @@
 # Board Installation Guidelines: Intel® FPGA SmartNIC N6000/1-PL, Intel® FPGA PAC D5005
 
-Last updated: **March 20, 2024** 
+Last updated: **May 06, 2024** 
 
 ## 1.0 Introduction
 
@@ -73,10 +73,10 @@ The following table provides a picture reference for the hardware components dis
 
 | Component | Image |
 | --------- | ------- |
-| Intel® FPGA SmartNIC N6001-PL (SKU2) | ![HARDWARE_1_N6000](images/HARDWARE_1_N6000.png) |
-| Supermicro Server SYS-220HE | ![HARDWARE_2_SERVER](images/HARDWARE_2_SERVER.png)|
-| Intel FPGA Download Cable II (Only Required for manual flashing) |![HARDWARE_3_JTAG](images/HARDWARE_3_JTAG.png) |
-| 2x5 Extension header - Samtech Part No: ESQ-105-13-L-D (Only Required for manual flashing) |![HARDWARE_4_EXTENDER](images/HARDWARE_4_EXTENDER.png) |
+| Intel® FPGA SmartNIC N6001-PL (SKU2) | ![HARDWARE_1_N6000](../../hw/common/board_installation/adp_board_installation/images/HARDWARE_1_N6000.png) |
+| Supermicro Server SYS-220HE | ![HARDWARE_2_SERVER](../adp_board_installation/images/HARDWARE_2_SERVER.png)|
+| Intel FPGA Download Cable II (Only Required for manual flashing) |![HARDWARE_3_JTAG](../../hw/common/board_installation/adp_board_installation/images/HARDWARE_3_JTAG.png) |
+| 2x5 Extension header - Samtech Part No: ESQ-105-13-L-D (Only Required for manual flashing) |![HARDWARE_4_EXTENDER](../../hw/common/board_installation/adp_board_installation/images/HARDWARE_4_EXTENDER.png) |
 
 In addition to the above, all OFS ADP platforms require an auxillary power cable for the 12 V-Auxiliary 2x4 PCIe* power connector. This cable will differ between server vendors - review the pinout of the power connector on the [Intel® FPGA Programmable Acceleration Card D5005 Data Sheet](https://www.intel.com/content/www/us/en/docs/programmable/683568/current/power.html) or [Intel FPGA SmartNIC N6001-PL Data Sheet - SKU2](https://www.intel.com/content/www/us/en/search.html?ws=text#q=n6001%20data%20sheet&sort=relevancy) (content ID=723837) as a reference for ordering. Although this is *not always the case*, often the standard 2x4 PCIe power connector that is required to enable a GPU in your server will also work for an FPGA-based ADP.
 
@@ -158,7 +158,7 @@ Please refer to sections 8.1 and 8.2 of the [Intel FPGA Programmable Acceleratio
 
 The Intel N6000/1-PL FPGA SmartNIC Platforms are officially verified in the upper middle PCIe x16 slot (Slot 3). If using a different slot, refer to the information in [Table 5 PCIe Slot Mapping](#table-5-pcie-slot-mapping) for which port settings to change in server BIOS.
 
-![SERVER_1](images/SERVER_1.png)
+![SERVER_1](../../hw/common/board_installation/adp_board_installation/images/SERVER_1.png)
 
 #### Table 5: PCIe Slot Mapping
 
@@ -176,7 +176,7 @@ The following instructions will help to ensure safe installation of an ADP platf
 1. Position the board over the selected connector on the motherboard.
 2. Press down gently and firmly to seat the card in the PCIe slot, and then secure the bracket to the system chassis with the retention screw.
 
-![SERVER_2](images/SERVER_2.png)
+![SERVER_2](../../hw/common/board_installation/adp_board_installation/images/SERVER_2.png)
 
 #### Table 6: ADP Installation Procedure
 
@@ -189,7 +189,7 @@ The following instructions will help to ensure safe installation of an ADP platf
 
 Do not bend the card while inserting into a slot. Do not apply much pressure in regions 2 or 3 while inserting.
 
-![SERVER_3](images/SERVER_3.png)
+![SERVER_3](../../hw/common/board_installation/adp_board_installation/images/SERVER_3.png)
 
 ### 4.3 Removal Procedure for The Intel® FPGA PAC D5005 and Intel® FPGA SmartNIC N6000/1-PL into a Server
 
@@ -199,7 +199,7 @@ The following instructions will help to ensure safe removal of the platforms fro
 2. Remove the retention bracket screw.
 3. Carefully lift the card out of the PCIe slot.
 
-![SERVER_4](images/SERVER_4.png)
+![SERVER_4](../../hw/common/board_installation/adp_board_installation/images/SERVER_4.png)
 
 #### Table 7: ADP Removal Procedure
 
@@ -211,4 +211,4 @@ The following instructions will help to ensure safe removal of the platforms fro
 
 Do not bend the card while removing it from the slot.
 
-![SERVER_5](images/SERVER_5.png)
+![SERVER_5](../../hw/common/board_installation/adp_board_installation/images/SERVER_5.png)

docs/hw/common/board_installation/devkit_board_installation/devkit_board_installation_guidelines.md

@@ -1,6 +1,6 @@
 # Board Installation Guidelines: Intel Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) and Intel Agilex® 7 FPGA I-Series Development Kit (2x R-Tile and 1xF-Tile)
 
-Last updated: **March 20, 2024** 
+Last updated: **May 06, 2024** 
 
 ## 1.0 Introduction
 
@@ -58,9 +58,9 @@ The information in this document is intended for customers evaluating the PCIe A
 
 ### 1.3 Required Hardware for Installation
 
-#### Table 2: Hardware BKC for OFS PCIe Attach targeting the F-tile Development Kit
+#### Table 2: Hardware BKC for OFS PCIe Attach targeting the F-Series Development Kit
 
-The following table highlights the hardware which composes the Best Known Configuation (BKC) for the OFS 2024.1 PCIe Attach release targeting F-tile Development Kit.
+The following table highlights the hardware which composes the Best Known Configuation (BKC) for the OFS 2024.1-1 PCIe Attach release targeting F-Series Development Kit.
 
 *Note: The Dell R750 server product line is known not to work with this release.*
 
@@ -102,45 +102,45 @@ The recommended fan speed setting is to use the 100% preset. If using a differen
 
 ## 3.0 Development Kit Installation
 
-### 3.1 Preparing the F-tile Development Kit for Installation into a Server
+### 3.1 Preparing the F-Series Development Kit for Installation into a Server
 
 Light pipes located on the top of the QSFP cages for the F-Series Dev Kit may or may not cause physical fit issues for some server platforms. If you run into any issues during installation you may remove the light pipes:
 
 1. The DK-DEV-AGF027F1ES (or it is called the F - tile Dev Kit, or FM86 Dev Kit) has LED light pipes on top of the QSFP cages.
 
-    ![ftile_qsfp_light_pipe](./images/ftile_qsfp_light_pipe.png)
+    ![ftile_qsfp_light_pipe](../../hw/common/board_installation/devkit_board_installation/images/ftile_qsfp_light_pipe.png)
 
     These light pipes interfere with the server PCIe slot faceplate.
 
-    ![ftile_qsfp_light_pipe_interference_r750](./images/ftile_qsfp_light_pipe_interference_r750.png)
+    ![ftile_qsfp_light_pipe_interference_r750](../../hw/common/board_installation/devkit_board_installation/images/ftile_qsfp_light_pipe_interference_r750.png)
 
 2. The light pipes can be easily removed by prying them off using a small screwdriver for leverage, then pushing the light pipes back to remove the retaining clips from the QSFP cage.
 
-    ![ftile_qsfp_light_pipe_removal_part1](./images/ftile_qsfp_light_pipe_removal_part1.png)
+    ![ftile_qsfp_light_pipe_removal_part1](../../hw/common/board_installation/devkit_board_installation/images/ftile_qsfp_light_pipe_removal_part1.png)
 
-    ![ftile_qsfp_light_pipe_removal_part2](./images/ftile_qsfp_light_pipe_removal_part2.png)
+    ![ftile_qsfp_light_pipe_removal_part2](../../hw/common/board_installation/devkit_board_installation/images/ftile_qsfp_light_pipe_removal_part2.png)
 
-    ![ftile_qsfp_light_pipe_removal_part3](./images/ftile_qsfp_light_pipe_removal_part3.png)
+    ![ftile_qsfp_light_pipe_removal_part3](../../hw/common/board_installation/devkit_board_installation/images/ftile_qsfp_light_pipe_removal_part3.png)
 
 ### 3.2 Default Switch Settings
 
 Double check that your development kit switch settings match those listed as the default positions in the user guide prior to installation. An F Tile Dev Kit is used as an example in this section.
 
 1. Board switch definitions can be found in the [Intel Agilex® 7 F-Series FPGA (Two F-Tiles) Development Kit User Guide](https://www.intel.com/content/www/us/en/docs/programmable/739942/current/overview.html) or [Intel Agilex® 7 FPGA I-Series Development Kit User Guide](https://www.intel.com/content/www/us/en/docs/programmable/683288/current/default-setting.html).
 
-    ![ftile_board_switches_diagram](./images/ftile_board_switches_diagram.png)
+    ![ftile_board_switches_diagram](../../hw/common/board_installation/devkit_board_installation/images/ftile_board_switches_diagram.png)
 
     See the image below for SW1, SW4 and SW3.
 
-    ![](./images/ftile_board_switches_picture.png)
+    ![](../../hw/common/board_installation/devkit_board_installation/images/ftile_board_switches_picture.png)
 
     Before inserting into a server, set SW5 to 'ON'.
 
-    ![ftile_board_sw5_on](./images/ftile_board_sw5_on.png)
+    ![ftile_board_sw5_on](../../hw/common/board_installation/devkit_board_installation/images/ftile_board_sw5_on.png)
 
 2. Below shows an F-Series Dev Kit installed into a PCIe riser with the light pipes removed.
 
-    ![ftile_final_installation_r750](./images/ftile_final_installation_r750.png)
+    ![ftile_final_installation_r750](../../hw/common/board_installation/devkit_board_installation/images/ftile_final_installation_r750.png)
 
 ### 3.3 Physical Installation Procedure
 
@@ -165,7 +165,7 @@ Steps:
 
 1. Refer to the following figure for Steps 2 and 3.
 
-  ![agilex_ftile_dev_kit](images/agilex_ftile_dev_kit.png)
+  ![agilex_ftile_dev_kit](../../hw/common/board_installation/devkit_board_installation/images/agilex_ftile_dev_kit.png)
 
 2. Locate Single DIP Switch **SW2** and 4-position DIP switch **SW3** on the fseries-dk. These switches control the JTAG setup for the board. Ensure that both **SW2** and **SW3.3** are set to `ON`.
 

docs/hw/common/board_installation/f2000x_board_installation/f2000x_board_installation.md

@@ -1,18 +1,18 @@
-# Board Installation Guidelines: Intel® IPU Platform F2000X-PL
+# Board Installation Guidelines: IPU Platform F2000X-PL
 
-Last updated: **March 20, 2024** 
+Last updated: **May 06, 2024** 
 
 ## 1.0 About this Document
 
-The purpose of this document is to help users prepare their server and install the Intel® IPU Platform F2000X-PL. After reviewing this document, a user shall be able to:
+The purpose of this document is to help users prepare their server and install the IPU Platform F2000X-PL. After reviewing this document, a user shall be able to:
 
 - Set up their server environment according to the Best Known Configuration (BKC)
 - Install an F2000X device into a supported server platform
 - Attach all required peripherals
 
 ### 1.1 Audience
 
-The information in this document is intended for customers evaluating the Intel® IPU Platform F2000X-PL. The card is an acceleration development platform (ADP) intended to be used as a starting point for evaluation and development. This document will cover key topics related to server bring-up and physical platform installation, with links for deeper dives on the topics discussed therein.
+The information in this document is intended for customers evaluating the IPU Platform F2000X-PL. The card is an acceleration development platform (ADP) intended to be used as a starting point for evaluation and development. This document will cover key topics related to server bring-up and physical platform installation, with links for deeper dives on the topics discussed therein.
 
 *Note: Code command blocks are used throughout the document. Comments are preceded with '#'. Full command output may not be shown.*
 
@@ -61,7 +61,7 @@ The information in this document is intended for customers evaluating the Intel
 
 ### 1.2 Server Requirements
 
-The following requirements must be met when purchasing a server to support the Intel® IPU Platform F2000X-PL.
+The following requirements must be met when purchasing a server to support the IPU Platform F2000X-PL.
 
 #### 1.2.1 Host Server Specifications
 
@@ -72,7 +72,7 @@ The host server must meet the following minimal specifications:
 
 #### 1.2.2 Host BIOS
 
-Te Host BIOS settings known to work with the Intel® IPU Platform F2000X-PL:
+Te Host BIOS settings known to work with the IPU Platform F2000X-PL:
 
 - PCIe slot width must be **x16**
 - PCIe slot speed must be **4**
@@ -85,11 +85,11 @@ Specific BIOS paths are not listed here, as they can differ between BIOS vendors
 
 While many host Linux kernel and OS distributions may work with this design, only the following configuration(s) have been tested:
 
-- Ubuntu 22.04, 6.1-lts
+- Ubuntu 22.04 LTS, 6.1.78-dfl
 
 ### 1.3 Server Forced Air Cooling
 
-The Intel® IPU Platform F2000X-PL is a high-performance processing card with a
+The IPU Platform F2000X-PL is a high-performance processing card with a
 passive heat sink to dissipate device heat and must be installed
 in a server with sufficient forced airflow cooling to keep all devices
 operating below maximum temperature. The table below lists the
@@ -101,13 +101,13 @@ thermal terms and descriptions used in thermal analysis.
 | ---                         |  ---                                  |
 | Cubic Feet per Minute (CFM) | Volumetric airflow rate, in cubic feet per minute, of air passing through faceplate. |
 | T<sub>j</sub>                        | FPGA Junction Temperature             |
-| T<sub>LA</sub>                       | Local Ambient temperature. Temperature of forced air as it enters the Intel® IPU Platform F2000X-PL. &nbsp; **Note:** In many systems, this is higher than the room ambient due to  heating effects of chassis components.  |
+| T<sub>LA</sub>                       | Local Ambient temperature. Temperature of forced air as it enters the IPU Platform F2000X-PL. &nbsp; **Note:** In many systems, this is higher than the room ambient due to  heating effects of chassis components.  |
 
 **Note:** The FPGA junction temperature must not exceed 100°C. The case
 temperature of the QSFP modules must meet the module vendor's
 specification.
 
-**Note:** The table below provides the thermal targets for which the Intel® IPU Platform F2000X-PL
+**Note:** The table below provides the thermal targets for which the IPU Platform F2000X-PL
 was designed. As a card manufacturer, you must
 qualify your own production cards.
 
@@ -118,12 +118,12 @@ The airflow requirements for optimal heat sink performance at minimum is
 characteristic of CAT 3 servers or PCIe SIG Level 7 thermal profiles, in
 both, forward & reverse flow, see figure below:
 
-![](./images/air_temp_vs_flowrate.PNG) ![](./images/modified_pcie_sig.png)
+![](../../hw/common/board_installation/f2000x_board_installation/images/air_temp_vs_flowrate.PNG) ![](../../hw/common/board_installation/f2000x_board_installation/images/modified_pcie_sig.png)
 
-As the Intel® IPU Platform F2000X-PL is a development platform, it is not
+As the IPU Platform F2000X-PL is a development platform, it is not
 integrated into the server baseband management controller closed loop
 cooling control. It is strongly recommended that you set your server's
-fan settings to run constantly at 100% with the server chassis lid closed to prevent unwanted Intel® IPU Platform F2000X-PL thermal shutdown.
+fan settings to run constantly at 100% with the server chassis lid closed to prevent unwanted IPU Platform F2000X-PL thermal shutdown.
 
 ### 1.4 External Connections
 
@@ -143,7 +143,7 @@ The items listed Table 6 in are known to work for external connectivity. Specifi
 |QSFP DAC Cable             |                         FS.com Generic 2m 100G QSP28 Passive Direct Attach Copper |  [QSFP28 DAC](https://www.fs.com/products/74661.html?attribute=10134&id=197229)|
 |(optional) Intel FPGA Download Cable II            |           PL-USB2-BLASTER                  |                            [USB-Blaster II](https://www.intel.com/content/www/us/en/products/sku/215664/intel-fpga-download-cable-ii/specifications.html)|
 
-### 1.5 Preparing the Intel® IPU Platform F2000X-PL for Installation
+### 1.5 Preparing the IPU Platform F2000X-PL for Installation
 
 Turn the board over to back side and remove the Kapton tape covering
 switches **SW2** and **SW3** and make sure the switches are set as shown in
@@ -165,7 +165,7 @@ switches **SW2** and **SW3** and make sure the switches are set as shown in
 
 #### 1.5.1 USB to Serial Adapter
 
-The Intel® IPU Platform F2000X-PL has a serial UART for access located on
+The IPU Platform F2000X-PL has a serial UART for access located on
 back edge of the board. This connection is useful for making BIOS and
 boot settings and for monitoring the SoC. In most servers, you will need
 to remove a riser card and route the USB to serial cable and (optional) Intel FPGA
@@ -185,7 +185,7 @@ is TXD, Black wire is ground and Green wire is RXD.
 
 #### 1.5.2 IPU JTAG
 
-The Intel® IPU Platform F2000X-PL provides a 10 pin JTAG header for FPGA and
+The IPU Platform F2000X-PL provides a 10 pin JTAG header for FPGA and
 Cyclone 10 Board Management Controller development work using a [Intel
 FPGA Download Cable
 II](https://www.intel.com/content/www/us/en/products/sku/215664/intel-fpga-download-cable-ii/specifications.html).
@@ -204,12 +204,12 @@ riser while programming.
 
 #### 1.5.3 Power
 
-The Intel® IPU Platform F2000X-PL must receive power from both the 12 V and 3.3V
+The IPU Platform F2000X-PL must receive power from both the 12 V and 3.3V
 PCIe slot and the 12 V Auxiliary 2×4 power connector. The board does not power up if any of the 12 V and 3.3 V PCIe slot,
 or 12 V Auxiliary power sources are disconnected.
 
 PCIe specifications define 12 V Auxiliary power connector pin
-assignment. The Intel® IPU Platform F2000X-PL implements an 8-position right
+assignment. The IPU Platform F2000X-PL implements an 8-position right
 angle (R/A) through-hole PCB header assembly on the top right side of
 the board as depicted in the picture below.
 
@@ -253,7 +253,7 @@ hub. See *Figure 9*.
 Connect your flash drive to an available Linux host. In this section the USB will set up to be used as a secondary boot source for the SoC and will also be used to update the NVMe from which the ICX-D SoC boots in section [2.1 Updating the F2000X-PL ICX-D SoC NVMe](#21-updating-the-f2000x-pl-icxd-soc-nvme).
 
 You will load the latest pre-compiled Yocto `core-image-minimal` WIC image into USB flash. This image can be downloaded from
-[2023.3 OFS Release for Agilex 7 SoC Attach Reference Shell](https://github.com/OFS/ofs-f2000x-pl/releases/tag/ofs-2024.1-1), under assets, or compiled from [meta-ofs](https://github.com/OFS/meta-ofs/releases/tag/ofs-2024.1-2). Compilation is discussed in section [4.0 Compiling a Custom Yocto SoC Image](#40-compiling-a-custom-yocto-soc-image).
+[ofs-2024.1-1 Release for Agilex 7 SoC Attach Reference Shell](https://github.com/OFS/ofs-f2000x-pl/releases/tag/ofs-2024.1-1), under assets, or compiled from [meta-ofs](https://github.com/OFS/meta-ofs/releases/tag/ofs-2024.1-2). Compilation is discussed in section [4.0 Compiling a Custom Yocto SoC Image](#40-compiling-a-custom-yocto-soc-image).
 
 1. Insert a 64 GB or larger USB Flash Drive into the USB slot of a computer/server you can use to format the drive. The following instructions assume you are using some flavor of GNU+Linux. You need sudo access privileges on this machine.
 
@@ -361,4 +361,4 @@ You will load the latest pre-compiled Yocto `core-image-minimal` WIC image into
     $ cp core-image-full-cmdline-intel-corei7-64-20240227185330.rootfs.wic /mnt
     ```
 
-Remove the USB flash from the Linux computer and install the flash drive in the USB hub attached to the Intel® IPU Platform F2000X-PL.
+Remove the USB flash from the Linux computer and install the flash drive in the USB hub attached to the IPU Platform F2000X-PL.