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diff --git a/docs/d5005/adp_board_installation_guidelines.md b/docs/d5005/adp_board_installation_guidelines.md
diff --git a/docs/d5005/sw_install_pcie_attach.md b/docs/d5005/sw_install_pcie_attach.md
diff --git a/docs/d5005/ug_dev_afu_sim_env.md b/docs/d5005/ug_dev_afu_sim_env.md
diff --git a/docs/d5005/ug_dev_pim_based_afu.md b/docs/d5005/ug_dev_pim_based_afu.md
diff --git a/docs/d5005/ug_docker.md b/docs/d5005/ug_docker.md
diff --git a/docs/d5005/ug_kvm.md b/docs/d5005/ug_kvm.md
diff --git a/docs/f2000x/sw_install_soc_attach.md b/docs/f2000x/sw_install_soc_attach.md
diff --git a/docs/f2000x/ug_dev_afu_sim_env.md b/docs/f2000x/ug_dev_afu_sim_env.md
diff --git a/docs/f2000x/ug_dev_pim_based_afu.md b/docs/f2000x/ug_dev_pim_based_afu.md
diff --git a/docs/f2000x/ug_docker.md b/docs/f2000x/ug_docker.md
diff --git a/docs/f2000x/ug_kvm.md b/docs/f2000x/ug_kvm.md
diff --git a/.../board_installation/adp_board_installation/adp_board_installation_guidelines.md b/.../board_installation/adp_board_installation/adp_board_installation_guidelines.md
@@ -1,6 +1,6 @@
 # Board Installation Guidelines: Intel® FPGA SmartNIC N6000/1-PL, Intel® FPGA PAC D5005
 
-Last updated: **March 20, 2024** 
+Last updated: **July 01, 2024** 
 
 ## 1.0 Introduction
 
@@ -60,7 +60,7 @@ The information in this document is intended for customers evaluating the PCIe A
 
 #### Table 2: Intel N6000/1-PL FPGA SmartNIC Platform SKU Mapping
 
-The following table highlights the differences between N6000/1 PL FPGA SmartNIC platforms (SKU1/SKU2). Use this table to identify which version of the N6000/1-PL FPGA SmartNIC platforms you have if you are unsure. The board identification printed by the `fpgainfo fme` commands depends on both the OPAE SDK and Linux DFL drivers from sections, whose installation is covered in the [Software Installation Guide: Open FPGA Stack for PCIe Attach](../../sw_installation/pcie_attach/sw_install_pcie_attach.md).
+The following table highlights the differences between N6000/1 PL FPGA SmartNIC platforms (SKU1/SKU2). Use this table to identify which version of the N6000/1-PL FPGA SmartNIC platforms you have if you are unsure. The board identification printed by the `fpgainfo fme` commands depends on both the OPAE SDK and Linux DFL drivers from sections, whose installation is covered in the [Software Installation Guide: OFS for PCIe Attach FPGAs].
 
 | SKU Mapping | SKU Value | Primary Difference| `fpgainfo` Identification|
 | --------- | ------- | ----- | ----- |
@@ -73,10 +73,10 @@ The following table provides a picture reference for the hardware components dis
 
 | Component | Image |
 | --------- | ------- |
-| Intel® FPGA SmartNIC N6001-PL (SKU2) | ![HARDWARE_1_N6000](images/HARDWARE_1_N6000.png) |
-| Supermicro Server SYS-220HE | ![HARDWARE_2_SERVER](images/HARDWARE_2_SERVER.png)|
-| Intel FPGA Download Cable II (Only Required for manual flashing) |![HARDWARE_3_JTAG](images/HARDWARE_3_JTAG.png) |
-| 2x5 Extension header - Samtech Part No: ESQ-105-13-L-D (Only Required for manual flashing) |![HARDWARE_4_EXTENDER](images/HARDWARE_4_EXTENDER.png) |
+| Intel® FPGA SmartNIC N6001-PL (SKU2) | ![HARDWARE_1_N6000](/ofs-2024.1-1/hw/common/board_installation/adp_board_installation/images/HARDWARE_1_N6000.png) |
+| Supermicro Server SYS-220HE | ![HARDWARE_2_SERVER](/ofs-2024.1-1/hw/common/board_installation/adp_board_installation/images/HARDWARE_2_SERVER.png)|
+| Intel FPGA Download Cable II (Only Required for manual flashing) |![HARDWARE_3_JTAG](/ofs-2024.1-1/hw/common/board_installation/adp_board_installation/images/HARDWARE_3_JTAG.png) |
+| 2x5 Extension header - Samtech Part No: ESQ-105-13-L-D (Only Required for manual flashing) |![HARDWARE_4_EXTENDER](/ofs-2024.1-1/hw/common/board_installation/adp_board_installation/images/HARDWARE_4_EXTENDER.png) |
 
 In addition to the above, all OFS ADP platforms require an auxillary power cable for the 12 V-Auxiliary 2x4 PCIe* power connector. This cable will differ between server vendors - review the pinout of the power connector on the [Intel® FPGA Programmable Acceleration Card D5005 Data Sheet](https://www.intel.com/content/www/us/en/docs/programmable/683568/current/power.html) or [Intel FPGA SmartNIC N6001-PL Data Sheet - SKU2](https://www.intel.com/content/www/us/en/search.html?ws=text#q=n6001%20data%20sheet&sort=relevancy) (content ID=723837) as a reference for ordering. Although this is *not always the case*, often the standard 2x4 PCIe power connector that is required to enable a GPU in your server will also work for an FPGA-based ADP.
 
@@ -158,7 +158,7 @@ Please refer to sections 8.1 and 8.2 of the [Intel FPGA Programmable Acceleratio
 
 The Intel N6000/1-PL FPGA SmartNIC Platforms are officially verified in the upper middle PCIe x16 slot (Slot 3). If using a different slot, refer to the information in [Table 5 PCIe Slot Mapping](#table-5-pcie-slot-mapping) for which port settings to change in server BIOS.
 
-![SERVER_1](images/SERVER_1.png)
+![SERVER_1](/ofs-2024.1-1/hw/common/board_installation/adp_board_installation/images/SERVER_1.png)
 
 #### Table 5: PCIe Slot Mapping
 
@@ -176,7 +176,7 @@ The following instructions will help to ensure safe installation of an ADP platf
 1. Position the board over the selected connector on the motherboard.
 2. Press down gently and firmly to seat the card in the PCIe slot, and then secure the bracket to the system chassis with the retention screw.
 
-![SERVER_2](images/SERVER_2.png)
+![SERVER_2](/ofs-2024.1-1/hw/common/board_installation/adp_board_installation/images/SERVER_2.png)
 
 #### Table 6: ADP Installation Procedure
 
@@ -189,7 +189,7 @@ The following instructions will help to ensure safe installation of an ADP platf
 
 Do not bend the card while inserting into a slot. Do not apply much pressure in regions 2 or 3 while inserting.
 
-![SERVER_3](images/SERVER_3.png)
+![SERVER_3](/ofs-2024.1-1/hw/common/board_installation/adp_board_installation/images/SERVER_3.png)
 
 ### 4.3 Removal Procedure for The Intel® FPGA PAC D5005 and Intel® FPGA SmartNIC N6000/1-PL into a Server
 
@@ -199,7 +199,7 @@ The following instructions will help to ensure safe removal of the platforms fro
 2. Remove the retention bracket screw.
 3. Carefully lift the card out of the PCIe slot.
 
-![SERVER_4](images/SERVER_4.png)
+![SERVER_4](/ofs-2024.1-1/hw/common/board_installation/adp_board_installation/images/SERVER_4.png)
 
 #### Table 7: ADP Removal Procedure
 
@@ -211,4 +211,4 @@ The following instructions will help to ensure safe removal of the platforms fro
 
 Do not bend the card while removing it from the slot.
 
-![SERVER_5](images/SERVER_5.png)
+![SERVER_5](/ofs-2024.1-1/hw/common/board_installation/adp_board_installation/images/SERVER_5.png)
diff --git a/..._installation/devkit_board_installation/devkit_board_installation_guidelines.md b/..._installation/devkit_board_installation/devkit_board_installation_guidelines.md
@@ -1,6 +1,6 @@
 # Board Installation Guidelines: Intel Agilex® 7 FPGA F-Series Development Kit (2x F-Tile) and Intel Agilex® 7 FPGA I-Series Development Kit (2x R-Tile and 1xF-Tile)
 
-Last updated: **March 20, 2024** 
+Last updated: **July 01, 2024** 
 
 ## 1.0 Introduction
 
@@ -58,9 +58,9 @@ The information in this document is intended for customers evaluating the PCIe A
 
 ### 1.3 Required Hardware for Installation
 
-#### Table 2: Hardware BKC for OFS PCIe Attach targeting the F-tile Development Kit
+#### Table 2: Hardware BKC for OFS PCIe Attach targeting the F-Series Development Kit
 
-The following table highlights the hardware which composes the Best Known Configuation (BKC) for the OFS 2024.1 PCIe Attach release targeting F-tile Development Kit.
+The following table highlights the hardware which composes the Best Known Configuation (BKC) for the OFS 2024.1-1 PCIe Attach release targeting F-Series Development Kit.
 
 *Note: The Dell R750 server product line is known not to work with this release.*
 
@@ -102,45 +102,44 @@ The recommended fan speed setting is to use the 100% preset. If using a differen
 
 ## 3.0 Development Kit Installation
 
-### 3.1 Preparing the F-tile Development Kit for Installation into a Server
+### 3.1 Preparing the F-Series Development Kit for Installation into a Server
 
 Light pipes located on the top of the QSFP cages for the F-Series Dev Kit may or may not cause physical fit issues for some server platforms. If you run into any issues during installation you may remove the light pipes:
 
 1. The DK-DEV-AGF027F1ES (or it is called the F - tile Dev Kit, or FM86 Dev Kit) has LED light pipes on top of the QSFP cages.
-    
-    ![ftile_qsfp_light_pipe](./images/ftile_qsfp_light_pipe.png)
+
+    ![ftile_qsfp_light_pipe](/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/images/ftile_qsfp_light_pipe.png)
 
     These light pipes interfere with the server PCIe slot faceplate.
-
-    ![ftile_qsfp_light_pipe_interference_r750](./images/ftile_qsfp_light_pipe_interference_r750.png)
+    ![ftile_qsfp_light_pipe_interference_r750](/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/images/ftile_qsfp_light_pipe_interference_r750.png)
 
 2. The light pipes can be easily removed by prying them off using a small screwdriver for leverage, then pushing the light pipes back to remove the retaining clips from the QSFP cage.
 
-    ![ftile_qsfp_light_pipe_removal_part1](./images/ftile_qsfp_light_pipe_removal_part1.png)
+    ![ftile_qsfp_light_pipe_removal_part1](/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/images/ftile_qsfp_light_pipe_removal_part1.png)
 
-    ![ftile_qsfp_light_pipe_removal_part2](./images/ftile_qsfp_light_pipe_removal_part2.png)
+    ![ftile_qsfp_light_pipe_removal_part2](/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/images/ftile_qsfp_light_pipe_removal_part2.png)
 
-    ![ftile_qsfp_light_pipe_removal_part3](./images/ftile_qsfp_light_pipe_removal_part3.png)
+    ![ftile_qsfp_light_pipe_removal_part3](/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/images/ftile_qsfp_light_pipe_removal_part3.png)
 
 ### 3.2 Default Switch Settings
 
 Double check that your development kit switch settings match those listed as the default positions in the user guide prior to installation. An F Tile Dev Kit is used as an example in this section.
 
 1. Board switch definitions can be found in the [Intel Agilex® 7 F-Series FPGA (Two F-Tiles) Development Kit User Guide](https://www.intel.com/content/www/us/en/docs/programmable/739942/current/overview.html) or [Intel Agilex® 7 FPGA I-Series Development Kit User Guide](https://www.intel.com/content/www/us/en/docs/programmable/683288/current/default-setting.html).
 
-    ![ftile_board_switches_diagram](./images/ftile_board_switches_diagram.png)
+    ![ftile_board_switches_diagram](/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/images/ftile_board_switches_diagram.png)
 
     See the image below for SW1, SW4 and SW3.
 
-    ![](./images/ftile_board_switches_picture.png)
+    ![](/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/images/ftile_board_switches_picture.png)
 
     Before inserting into a server, set SW5 to 'ON'.
 
-    ![ftile_board_sw5_on](./images/ftile_board_sw5_on.png)
+    ![ftile_board_sw5_on](/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/images/ftile_board_sw5_on.png)
 
 2. Below shows an F-Series Dev Kit installed into a PCIe riser with the light pipes removed.
 
-    ![ftile_final_installation_r750](./images/ftile_final_installation_r750.png)
+    ![ftile_final_installation_r750](/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/images/ftile_final_installation_r750.png)
 
 ### 3.3 Physical Installation Procedure
 
@@ -157,15 +156,15 @@ Both Development Kits have an on-board FPGA Download Cable II module which is us
 
 Pre-requisites:
 
-* This walkthrough requires an OFS Agilex PCIe Attach deployment environment. Refer to the [Software Installation Guide: PCIe Attach](../../sw_installation/pcie_attach/sw_install_pcie_attach.md) for instructions on setting up a deployment environment.
+* This walkthrough requires an OFS Agilex PCIe Attach deployment environment. Refer to the [Software Installation Guide: PCIe Attach](https://ofs.github.io/ofs-2024.1-1/hw/common/sw_installation/pcie_attach/sw_install_pcie_attach.md) for instructions on setting up a deployment environment.
 
 * This walkthrough requires a workstation with Quartus Prime Pro Version 23.4 tools installed, specifically the `jtagconfig` tool.
 
 Steps:
 
 1. Refer to the following figure for Steps 2 and 3.
 
-  ![agilex_ftile_dev_kit](images/agilex_ftile_dev_kit.png)
+  ![agilex_ftile_dev_kit](/ofs-2024.1-1/hw/common/board_installation/devkit_board_installation/images/agilex_ftile_dev_kit.png)
 
 2. Locate Single DIP Switch **SW2** and 4-position DIP switch **SW3** on the fseries-dk. These switches control the JTAG setup for the board. Ensure that both **SW2** and **SW3.3** are set to `ON`.