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Inquiries about TEE memory #6160
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When
Each TA declares, when instancied, how much heap it requires (image +
When TEE_RAM size is given by See core/arch/arm/include/mm/generic_ram_layout.h.
Platforms testing pager ( Note a 128kB SRAM for OP-TEE with pager is quite a challenge. 256kB or more is recommended. |
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How to check the available TEE memory size when SBC boot? |
When core is built with
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This commit introduces the CFG_DRAM1_BASE configuration switch in the plat-hikey platform. This change aligns with previous discussions and resolves issues OP-TEE#5146, OP-TEE#4768, and OP-TEE#6160. Signed-off-by: zwb-233 <a1231512a@163.com>
This commit introduces the CFG_DRAM1_BASE configuration switch in the plat-hikey platform. This change aligns with previous discussions and resolves issues OP-TEE#5146, OP-TEE#4768, and OP-TEE#6160. Signed-off-by: Wen Bin <a1231512a@163.com>
I am studying memory in TEE, and I have a few questions.
I'm working on QEMU v8 environment. (CFG_WITH_PAGER=n)
CFG_TZDRAM_SIZE.
Refer to the generic_ram_layout.h file for details.
Checking TEE RAM layout without CFG_WITH_PAGER, there is TEE core secure RAM (TEE_RAM).
Does this include both the code area and data area of optee-os?
If so, the Trusted Application RAM (TA_RAM) seems to be the area for TA's code and data.
It is thought that several TAs share and use this area. I wonder how memory is managed when several TAs are running.
For example, if TA A has allocated a large amount of heap memory, and TA B also requests a large amount of heap, how is it managed?
I understand that general Linux systems are managed through PAGING and SWAP. In optee, is out of memory returned in the above situation or is there a separate management method?
The heap size of optee os is designated as "CFG_CORE_HEAP_SIZE" when building optee-os, and the heap size of TA is designated as property (TA_DATA_SIZE) when building TA.
Looking at TEE RAM layout without CFG_WITH_PAGER, it seems that there is no CFG_XXXX that distinguishes between TEE core secure RAM (TEE_RAM) and Trusted Application RAM (TA_RAM).
Is it used as contiguous memory as shown below?
If so, I think increasing the size of "CFG_CORE_HEAP_SIZE" will lower the maximum allowed value of TA_DATA_SIZE. Am I right?
And in the picture above, do other areas other than code and data exist?
I saw in the link below that it was written as a solution for SRAM 128 to 256 KiB environment.
https://optee.readthedocs.io/en/latest/architecture/core.html#pager
Again, I'm studying on QEMU v8 right now, and I've confirmed that CFG_WITH_PAGER=n is set.
BR,
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