arm: pl310: fix cache sync #2035
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Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
I think we should wait for feedback from @etienne-lms too.
| @@ -96,7 +96,7 @@ loop_cli_sync: | |||
| cmp r1, #0 | |||
| bne loop_cli_sync | |||
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Not strictly related to the change. Is this loop needed?
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If only PL310 is supported, it loop is not needed. L220 needs that loop :) Keep that loop for PL310 seems no harm.
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Thanks for the explanation. A comment in the code would be welcome. :-)
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@jenswi-linaro Updated with your tags applied and comments added. @etienne-lms do you have comments? |
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No comment but looks good, even better than before since PL310 cache_sync seems to expect being written to 0 not 1. |
According to PL310 TRM:
Atomic operations:
The following are atomic operations:
Clean Line by PA or by Set/Way
Invalidate Line by PA
Clean and Invalidate Line by PA or by Set/Way
Cache Sync.
These operations stall the slave ports until they are complete.
When these registers are read, bit [0], the C flag, indicates that
a background operation is in progress. When written, bit 0 must be
zero.
So write 1 to sync register is not correct.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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Updated with Tags applied. Thanks. |
According to PL310 TRM:
Atomic operations:
The following are atomic operations:
Clean Line by PA or by Set/Way
Invalidate Line by PA
Clean and Invalidate Line by PA or by Set/Way
Cache Sync.
These operations stall the slave ports until they are complete.
When these registers are read, bit [0], the C flag, indicates that
a background operation is in progress. When written, bit 0 must be
zero.
So write 1 to sync register is not correct.
Signed-off-by: Peng Fan peng.fan@nxp.com