Scope

HDL/Makefile

@@ -15,7 +15,9 @@ CORES_PAVEL = axi_axis_reader_v1_0 axi_axis_writer_v1_0 axi_bram_reader_v1_0 \
         axis_zeroer_v1_0 axis_variable_v1_0 axis_interpolator_v1_0 \
         axi_sts_register_v1_0
 
-CORES = micro_sequencer_v1_0 axi_dac_spi_sequencer_v1_1 axi_dac_daisy_spi_sequencer_v1_0 axis_segmented_bram_reader_v1_0 axi_serial_attenuator_v1_0 axi_four_ltc2656_spi_v1_0 axi_trigger_core_v1_0 axis_red_pitaya_adc_v3_0 axi_config_registers_v1_0
+CORES = micro_sequencer_v1_1 axi_dac_spi_sequencer_v1_1 axi_dac_daisy_spi_sequencer_v1_0 axis_segmented_bram_reader_v1_1 axi_serial_attenuator_v1_0 axi_four_ltc2656_spi_v1_0 axi_trigger_core_v1_0 axis_red_pitaya_adc_v3_0 \
+axi_config_registers_v1_0 axis_dma_rx_v1_0 axi_sniffer_v1_0 axis_red_pitaya_adc_ddr_v1_0 red_pitaya_adc_spi_v1_0 axis_acq_trigger_v1_0 axis_red_pitaya_adc_2ch_v1_0 \
+axis_rx_trigger_v1_0 axi_lite_master_v1_0
 
 VIVADO = vivado -nolog -nojournal -mode batch
 HSI = xsct
@@ -68,7 +70,9 @@ $(DTREE_DIR):
 	git --git-dir $@/.git --work-tree $@ checkout $(DTREE_TAG)
 
 tmp/%.dtbo: tmp/$(BOARD)_$(NAME).tree/system.dts
-	dtc -O dtb -o tmp/$(BOARD)_$(NAME).dtbo -b 0 -@ tmp/$(BOARD)_$(NAME).tree/pl.dtsi
+	sed -i 's/#address-cells = <2>;/#address-cells = <1>;/g' tmp/$(BOARD)_$(NAME).tree/pl.dtsi
+	sed -i 's/#size-cells = <2>;/#size-cells = <1>;/g' tmp/$(BOARD)_$(NAME).tree/pl.dtsi
+	dtc -O dtb -o tmp/$(BOARD)_$(NAME).dtbo -b 0 -@ devicetree/$(BOARD)_$(NAME).dtsi
 
 tmp/cores_pavel/%: cores_pavel/%/core_config.tcl cores_pavel/%/*.v
 	mkdir -p $(@D)

HDL/boards/stemlab_125_14/ocra_config.json

@@ -3,6 +3,6 @@
         "part": "xc7z010clg400-1",
         "proc": "ps7_cortexa9_0",
 	"board_part": "redpitaya.com:stemlab_125_14:part0:1.0",
-        "projects": ["ocra_mri", "shim_controller", "base_pl"]
+        "projects": ["ocra_mri", "shim_controller", "base_pl", "scope", "ex_data_transfer"]
     }
 }

HDL/boards/stemlab_125_14/pl_scope.json

@@ -0,0 +1,9 @@
+{
+    "mode": "ADVANCED",
+    "has_tx": "TRUE",
+    "modulated": "TRUE",
+    "rx_channel_count": "2",
+    "fclk_source": "SATA",
+    "device_class_id": "0x00001002",
+    "device_version": "0x00000004"
+}

HDL/boards/stemlab_125_14/ports.tcl

@@ -41,3 +41,9 @@ create_bd_port -dir IO -from 7 -to 0 exp_n_tri_io
 ### LED
 
 create_bd_port -dir O -from 7 -to 0 led_o
+
+### SATA Connector
+create_bd_port -dir I sata_s2_a_p
+create_bd_port -dir I sata_s2_a_n
+create_bd_port -dir I sata_s2_b_p
+create_bd_port -dir I sata_s2_b_n

HDL/boards/stemlab_125_14/ports.xdc

@@ -150,8 +150,8 @@ set_property SLEW FAST [get_ports {exp_p_tri_io[*]}]
 set_property SLEW FAST [get_ports {exp_n_tri_io[*]}]
 set_property DRIVE 8 [get_ports {exp_p_tri_io[*]}]
 set_property DRIVE 8 [get_ports {exp_n_tri_io[*]}]
-set_property PULLTYPE PULLUP [get_ports {exp_p_tri_io[*]}]
-set_property PULLTYPE PULLUP [get_ports {exp_n_tri_io[*]}]
+set_property PULLUP true [get_ports {exp_p_tri_io[*]}]
+set_property PULLUP true [get_ports {exp_n_tri_io[*]}]
 
 set_property PACKAGE_PIN G17 [get_ports {exp_p_tri_io[0]}]
 set_property PACKAGE_PIN G18 [get_ports {exp_n_tri_io[0]}]
@@ -186,24 +186,22 @@ set_property PACKAGE_PIN J16 [get_ports {exp_n_alex[2]}]
 set_property PACKAGE_PIN M15 [get_ports {exp_n_alex[3]}]
 
 ### SATA connector
-
-set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_p_o[*]]
-set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_n_o[*]]
-
-set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_p_i[*]]
-set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports daisy_n_i[*]]
-
-set_property PACKAGE_PIN T12 [get_ports {daisy_p_o[0]}]
-set_property PACKAGE_PIN U12 [get_ports {daisy_n_o[0]}]
-
-set_property PACKAGE_PIN U14 [get_ports {daisy_p_o[1]}]
-set_property PACKAGE_PIN U15 [get_ports {daisy_n_o[1]}]
-
-set_property PACKAGE_PIN P14 [get_ports {daisy_p_i[0]}]
-set_property PACKAGE_PIN R14 [get_ports {daisy_n_i[0]}]
-
-set_property PACKAGE_PIN N18 [get_ports {daisy_p_i[1]}]
-set_property PACKAGE_PIN P19 [get_ports {daisy_n_i[1]}]
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sata_s1_a_p];
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sata_s1_a_n];
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sata_s1_b_p];
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sata_s1_b_n];
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sata_s2_a_p];
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sata_s2_a_n];
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sata_s2_b_p];
+set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports sata_s2_b_n];
+set_property PACKAGE_PIN T12 [get_ports sata_s1_a_p];
+set_property PACKAGE_PIN U12 [get_ports sata_s1_a_n];
+set_property PACKAGE_PIN U14 [get_ports sata_s1_b_p]; #Clock Capable Input (SRCC)
+set_property PACKAGE_PIN U15 [get_ports sata_s1_b_n]; #Clock Capable Input (SRCC)
+set_property PACKAGE_PIN P14 [get_ports sata_s2_a_p];
+set_property PACKAGE_PIN R14 [get_ports sata_s2_a_n];
+set_property PACKAGE_PIN N18 [get_ports sata_s2_b_p]; #Clock Capable Input (MRCC)
+set_property PACKAGE_PIN P19 [get_ports sata_s2_b_n]; #Clock Capable Input (MRCC)
 
 ### LED
 

HDL/boards/stemlab_125_14/ps_ex_data_transfer.xml

@@ -0,0 +1,165 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE project PUBLIC "project" "project.dtd" >
+<project version="1.0" >
+  <description >
+  </description>
+  <Projinfo Part="xc7z010clg400-1" DeviceSize="xc7z010" Package="clg400" Speed="-1" />
+  <set param="PCW::S_AXI::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::ENET0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::ENET0::GRP_MDIO::ENABLE" value="1" />
+  <set param="PCW::ENET0::ENET0::IO" value="MIO 16 .. 27" />
+  <set param="PCW::ENET0::GRP_MDIO::IO" value="MIO 52 .. 53" />
+  <set param="PCW::GPIO::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::GPIO::MIO_GPIO::ENABLE" value="1" />
+  <set param="PCW::GPIO::EMIO_GPIO::ENABLE" value="1" />
+  <set param="PCW::I2C0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::I2C0::I2C0::IO" value="MIO 50 .. 51" />
+  <set param="PCW::I2C1::PERIPHERAL::ENABLE" value="0" />
+  <set param="PCW::UART0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::UART0::UART0::IO" value="MIO 14 .. 15" />
+  <set param="PCW::UART1::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::UART1::UART1::IO" value="MIO 8 .. 9" />
+  <set param="PCW::USB0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::USB0::RESET::ENABLE" value="1" />
+  <set param="PCW::USB0::RESET::IO" value="MIO 48" />
+  <set param="PCW::USB1::PERIPHERAL::ENABLE" value="0" />
+  <set param="PCW::QSPI::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::QSPI::GRP_SS1::ENABLE" value="0" />
+  <set param="PCW::QSPI::GRP_FBCLK::ENABLE" value="0" />
+  <set param="PCW::SD0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::SD0::GRP_CD::ENABLE" value="1" />
+  <set param="PCW::SD0::GRP_WP::ENABLE" value="1" />
+  <set param="PCW::SD0::GRP_CD::IO" value="MIO 46" />
+  <set param="PCW::SD0::GRP_WP::IO" value="MIO 47" />
+  <set param="PCW::SPI0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::SPI1::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::SPI1::SPI1::IO" value="MIO 10 .. 15" />
+  <set param="PCW::TTC0::PERIPHERAL::ENABLE" value="1" />
+  <set param="PCW::FPGA0::PERIPHERAL::FREQMHZ" value="143" />
+  <set param="PCW::CAN::PERIPHERAL::FREQMHZ" value="100" />
+  <set param="PCW::QSPI::PERIPHERAL::FREQMHZ" value="125" />
+  <set param="PCW::ENET0::PERIPHERAL::FREQMHZ" value="1000 Mbps" />
+  <set param="PCW::PRESET::FPGA::PARTNUMBER" value="xc7z010clg400-1" />
+  <set param="PCW::PRESET::FPGA::SPEED" value="-1" />
+  <set param="PCW::PRESET::BANK0::VOLTAGE" value="LVCMOS 3.3V" />
+  <set param="PCW::PRESET::BANK1::VOLTAGE" value="LVCMOS 2.5V" />
+  <set param="PCW::PRESET::GLOBAL::CONFIG" value="Default" />
+  <set param="PCW::PRESET::GLOBAL::DEFAULT" value="powerup" />
+  <set param="PCW::UIPARAM::DDR::PARTNO" value="MT41J256M16 RE-125" />
+  <set param="PCW::UIPARAM::DDR::BUS_WIDTH" value="16 Bit" />
+  <set param="PCW::UIPARAM::DDR::DRAM_WIDTH" value="16 Bits" />
+  <set param="PCW::UIPARAM::DDR::DEVICE_CAPACITY" value="4096 MBits" />
+  <set param="PCW::UIPARAM::DDR::SPEED_BIN" value="DDR3_1066F" />
+  <set param="PCW::UIPARAM::DDR::ROW_ADDR_COUNT" value="15" />
+  <set param="PCW::UIPARAM::DDR::CWL" value="6" />
+  <set param="PCW::UIPARAM::DDR::T_RC" value="48.91" />
+  <set param="PCW::UIPARAM::DDR::T_RAS_MIN" value="35.0" />
+  <set param="PCW::UIPARAM::DDR::T_FAW" value="40.0" />
+  <set param="PCW::MIO::MIO[0]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[0]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[1]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[2]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[3]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[4]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[5]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[6]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[7]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[8]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[8]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[9]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[9]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[10]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[11]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[12]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[13]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[14]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[15]::IOTYPE" value="LVCMOS 3.3V" />
+  <set param="PCW::MIO::MIO[16]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[16]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[16]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[16]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[17]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[17]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[17]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[17]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[18]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[18]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[18]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[18]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[19]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[19]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[19]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[19]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[20]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[20]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[20]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[20]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[21]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[21]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[21]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[21]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[22]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[22]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[22]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[22]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[23]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[23]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[23]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[23]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[24]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[24]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[24]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[24]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[25]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[25]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[25]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[25]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[26]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[26]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[26]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[26]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[27]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[27]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[27]::PULLUP" value="disabled" />
+  <set param="PCW::MIO::MIO[27]::DIRECTION" value="in" />
+  <set param="PCW::MIO::MIO[28]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[28]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[29]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[29]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[30]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[30]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[31]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[31]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[32]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[32]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[33]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[33]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[34]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[34]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[35]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[35]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[36]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[36]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[37]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[37]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[38]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[38]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[39]::SLEW" value="fast" />
+  <set param="PCW::MIO::MIO[39]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[40]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[41]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[42]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[43]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[44]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[45]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[46]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[47]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[48]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[49]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[50]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[51]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[52]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[52]::DIRECTION" value="out" />
+  <set param="PCW::MIO::MIO[53]::IOTYPE" value="LVCMOS 2.5V" />
+  <set param="PCW::MIO::MIO[53]::DIRECTION" value="inout" />
+</project>