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Add API for non-caching-load #1289

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RCCL provides "low latency" protocols for communication between agents, where the entire message consisting of data and flags is packed into a single L2 cache line. This is usually accomplished using atomic relaxed instructions in LLVM. But the 128-byte version of this protocol (LL-128) requires 128-bit load or store instructions that bypass the cache and are not broken up into multiple instructions. The nontemporal builtin is not always suitable for this use case.

The proposed approach is to provide a C++ function template that encapsulates an inline assembly call. This asm is intended to use the appropriate load/store parameters for each combination of data size and architecture.

@AlexVlx
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AlexVlx commented Aug 9, 2024

Have you actually verified that the byte two-byte load instructions you are using exist on the ISAs you expect them to exist? If you have, perhaps you want to check again, carefully, if they exist on GFX9 and GFX10? Has this been tested at all? Should it not have some unit tests in tow?

@ranapratap55 ranapratap55 force-pushed the ranapratap55/non-caching-load branch 2 times, most recently from 74cc26c to a52284b Compare October 8, 2024 05:20
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Have you actually verified that the byte two-byte load instructions you are using exist on the ISAs you expect them to exist? If you have, perhaps you want to check again, carefully, if they exist on GFX9 and GFX10? Has this been tested at all? Should it not have some unit tests in tow?

Updated the patch with byte, 2-byte load and added test cases.

@ranapratap55 ranapratap55 force-pushed the ranapratap55/non-caching-load branch 2 times, most recently from 81910cd to 6a5370a Compare October 8, 2024 05:30
@ranapratap55 ranapratap55 force-pushed the ranapratap55/non-caching-load branch from 6a5370a to 24372dc Compare October 15, 2024 05:18
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ping.

@wenkaidu
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3 participants