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SumaiyaTariqueLabiba/README.md

Hi, I’m Labiba!

  • I’m currently learning RTL DV methods and protocols.
  • I’m looking to collaborate on projects and research papers on technological advancements in VLSI Chip design, System Architecture, Verification methods, tools, protocols and more.
  • Contact me: Linkedin - https://www.linkedin.com/in/sumaiya-tarique-labiba

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  1. VeriRISC-CPU VeriRISC-CPU Public

    This project was developed based on the labs for Cadence certification on SystemVerilog for Design and Verification V21.10

    SystemVerilog 2 1

  2. SV-Verification SV-Verification Public

    Coverage, Assertions, Randomizations, Mailbox, Semaphores, DPI and OOP: Inheritance, Polymorphism, Virtual methods

    SystemVerilog 1

  3. SystemVerilog-Basics SystemVerilog-Basics Public

    FIFO, FSM, UART, RAM, ALU, etc.

    SystemVerilog 1