SumaiyaTariqueLabiba / VeriRISC-CPU Public

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This project was developed based on the labs for Cadence certification on SystemVerilog for Design and Verification V21.10

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Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
CPUtest1.dat		CPUtest1.dat
CPUtest2.dat		CPUtest2.dat
CPUtest3.dat		CPUtest3.dat
README.md		README.md
alu.sv		alu.sv
controller.sv		controller.sv
counter.sv		counter.sv
cpu_top.sv		cpu_top.sv
mem.sv		mem.sv
mux.sv		mux.sv
opcodes.sv		opcodes.sv
register.sv		register.sv
test_cpu.sv		test_cpu.sv

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VeriRISC-CPU

Tools: Cadence xcelium

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Test 1

Test 2

Test 3

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This project was developed based on the labs for Cadence certification on SystemVerilog for Design and Verification V21.10

cpu systemverilog cadence veririsc

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SystemVerilog 100.0%