Update to svd2rust 0.30.2 #1
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The Parts changed where adding SELECT to a few Registers ending with _A, as they were renamed frm *_A to *SELECT_A
…o Terminal (atsamd-rs#624) * Edited the Cargo.toml file to include a dependency for the snake game and also added code for the snake game under examples * Added entry for snake * Formatting changes for rustfmt * Added LED indicator to let player know that the game is over. Also made accidental self intersection by trivially changing direction to opposite impossible * Update CHANGELOG.md
* Nvm: Derive Copy and Clone for `nvm::Bank`
* Nvm: refactor focused on extending the userpage API
Overview:
- Make the NVM bitfield structs' methods public
- Add setters for the `Userpage` bitfield struct
- CalibrationArea and TemperaturesCalibrationArea do not need
setters as they cannot be modified.
- Extend the `Userpage` struct to cover the whole page (512 bytes)
- Split `Nvm::write` and `Nvm::erase` method into "main address space
flash" and "userpage flash" oriented APIs
- Add idempotent `Nvm::modify_userpage` (avoids unnecessary
flash erase & write)
Breaking changes:
- Switch to `*mut 32` from `u32` for address arguments
- `Nvm::userpage` -> `Nvm::read_userpage`
- `Nvm::write` -> `Nvm::write_flash`
- `Nvm::write_from_slice` -> `Nvm::write_flash_from_slice`
- `Nvm::erase` -> `Nvm::erase_flash`
Note:
Block erase granularity is assumed for main address space
flash erasure; thus `granularity` disappeared from the
signature.
* Nvm: expose extra commands and raw registers
New methods providing access to the following NVM commands
- SSB (Enable Security Bit)
- CELCK (Enable Chip-Erase Lock)
- CEULCK (Disable Chip-Erase Lock)
Also, expose unsafely underlying `NVMCTRL` register type as an
escape hatch (`Nvm::registers`).
* Add NVM API changes to CHANGELOG
* Refactor error handling in NVMCTRL
* Add `region_lock` API
* Fix and invert the condition
* Update CHANGELOG.md
* Clarify region lock doc comment
---------
Co-authored-by: Gabriel Górski <gabriel.gorski@volvocars.com>
This change keeps the register names in sync with the datasheet.
* Add defmt feature and derive error types (atsamd-rs#684)
* Make fugit obligatory dependency * Move time module to use fugit * prelude * timer_params * rtc * sercom::i2c * sercom::spi * sercom::uart * sleeping_delay * thumbv7em::clock::v2:dfll * thumbv7em::clock::v2::dpll * thumbv7em::clock::v2::gclk * thumbv7em::clock::v2::osculp32k * thumbv7em::clock::v2::rtcosc * thumbv7em::clock::v2::xosc * thumbv7em::clock::v2::xosc32k * thumbv7em::clock::v1 * thumbv7em::timer * thumbv7em::pwm * thumbv6m::clock * thumbv6m::timer * thumbv6m::pwm * delay * Add re-export of fugit * BSC Tier I Update * Update CHANGELOG * Update CAN related code
Overlooked example that failed to compile in atsamd-rs#672.
* Debug, Clone, Copy, Eq, PartialEq for all errors types
Co-authored-by: Adrian Geipert <adrian.git@geipert.eu>
- TC4 APB clock should be disabled by default
Prepare crates for v0.16.0 release
* Update atsamd-hal to 0.16 and add built-in pin definitions * Add LED and VBatt sensor pins. Update each of 3 examples to use new atsamd-hal API * Update version number and changelog * arduino_mkrzero: add blinky_rtic example Signed-off-by: Arne Kappen <arne.kappen@hhi.fraunhofer.de> * fix fmt Signed-off-by: Arne Kappen <arne.kappen@hhi.fraunhofer.de> * Update blinky RTIC example to work with latest BSP changes --------- Signed-off-by: Arne Kappen <arne.kappen@hhi.fraunhofer.de> Co-authored-by: Arne Kappen <arne.kappen@hhi.fraunhofer.de>
4 tasks
* Fix release HAL crate workflow * Fix pyportal nightly build
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atsamd-rs/masterand fix conflictscortex-m/critical-section-single-corefeature flag in PACs