FFT_ChipDesign

A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.

Features

Function

• Each input value is a complex number, divided into real and imaginary parts;
• Both the real and imaginary parts of inputs are 17 bits;
  • Bit 16 is the sign bit;
  • Bit 8-15 are decimal bits;
  • Bit 0-7 are integer bits.
• Both the real and imaginary parts of rotation factors are 8 bits;
  • Bit 8 is the sign bit;
  • Bit 0-7 are decimal bits;
  • No integer bits, the default is 0.
• Make sure that the FFT function is correct.

Evaluation index

Evaluation Index	Value
Process	SMIC 0.18 μm
Number of Pins	90
Operation frequency	135.135 MHz
Operation voltage	1.62 V
Total area	4.695300 mm2
Power consumption per calculate operation	5.25118208×10-6 mJ
FFT operands per unit area and unit power consumption	41987.688 times/(mm2·mW·s)
Bandwidth	510.51 MB/s
Parallel throughput	4.5946×109 bps

File Name	Type	Functional description
ctrl	Sequential	Control the data flow of the entire chip
s_p	Sequential	Integrate serial input data into parallel and change the order
mux	Sequential	Select the data entering the arithmetic module
reg1	Sequential	Store and forward operation data between two FFT stages
butterfly	Combinational	Perform 4-input butterfly operation
multi16	Combinational	Calculate the multiplication between the data and the rotation factor
p_s	Sequential	Integrate parallel output data into serial and change the order

Chip overview

Details

Principle and design

16-point radix-4 FFT schematic diagram

Hardware structure diagram

RTL model simulation verification

Modelsim single waveform

Modelsim multi-waveform

Logic Synthesis

DC reports

Physical realization and verification

Chip overview

PNA voltage drop

Congestion

Cell density

Finish screenshot

Team division

Member	Division of Work
Venci Freeman	Butterfly, multi selector and top module, DC and ICC.
Luo Tian	Conversion between series and parallel, register, DC and ICC.
Mike Qi	Control module, test bench and some tcl files, DC and ICC.

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Acknowledgement

• Frist of all, we want to thank Prof. He Weifeng, his course providing us with the opportunity to learn the complete chip design process, and he also answered the questions we encountered in detail in class. The twice-weekly discussion held by the him during the design workflow greatly helped us optimize our design of the chip and also taught us a lot.
• Then we want to thank the assistant Zhang Chao. The materials provided by him greatly helped us optimize the design of the chip, and he patiently answered all the unknown error messages we encountered throughout the workflow, which helped us a lot.
• And I would like to personally thank Zhang Jialing of Group 1 and Zhang Yunfang of Group 4 who also design FFT chips. Although the algorithms we adopt are different, their ideas also have reference value for our optimization. Especially when our design work frequency is too low in the early stage, their two sets of multiplier implementation solutions inspired us to optimize the multiplier.
• Finally, I would also like to thank other assistants and classmates who helped us complete the design and help the course go smoothly.
• In addition, when we didn't know the direction in the early stage, the work of others on GitHub and CSDN blog also gave us a lot of inspiration. I would like to thank you here.
• Our version management work is also implemented through GitHub. After the project achieved, we adopted the Mozilla 2.0 public license for open source, as a small contribution to the open source community.

References

[1] Garrido M, Huang S J, Chen S G. Feedforward FFT Hardware Architectures Based on Rotator Allocation[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2018, 65(2):581-592.

[2] Zulkifli, Siva. Design of 16-point Radix-4 Fast Fourier Transform in 0.18µm CMOS Technology. American Journal of Applied Sciences. 2007.

[3] 丁晓磊, 朱恩, 赵梅. 16点基4-FFT芯片设计技术研究[J]. 信息技术, 2007(01): 64-67+71.