SegFault in genrtlil

[ZipCPU]

I traced a segfault down to the current_ast->dumpAst(*) line below at line 1568 in genrtlil.cc. As far as I can tell, this was created from calling $past() on an object of zero width. (Yes, this is a bug, but Yosys shouldn't segfault on this bug. Fixing the width in the source file eliminated the segfault too.)

// everything should have been handled above -> print error if not.
default:
	for (auto f : log_files)
		current_ast->dumpAst(f, "verilog-ast> ");
	type_name = type2str(type);
	log_file_error(filename, linenum, "Don't know how to generate RTLIL code for %s node!\n", type_name.c_str());

Expected behavior

An error message indicating the line of code with a problem. (The simple test cases I've created to try to replicate this behavior have failed to do so.)

It seems as though under certain conditions (I'm not quite sure which), current_ast is never getting set. A further look into the source, suggests this call should be with respect to this and not current_ast--at least in those cases where current_ast is NULL. Changing current_ast to "this" fixed the problem and produced a valuable error message.

[ZipCPU]

Here's the design that caused the bug.

master_axi.zip

The obvious bug is that the widths of several items are zero. The segfault was the unexpected part.

[ZipCPU]

The proposed fix handles this bug. Thank you!