Update ad469x spi engine (#1181)

* Update ad469x spi engine

I replaced the SPI Engine connections in the ad469x_bd.tcl with the
spi_engine_create procedure found in the spi_engine.tcl script. Through
these changes, a more generic instantiation for the spi_engine can be
achieved. I also created the ad469x_fmc.txt file for generating the
system_constr.xdc file.

Signed-off-by: Ioan-daniel Pop <Pop.Ioan-daniel@analog.com>

projects/ad469x_fmc/Readme.md

@@ -2,10 +2,10 @@
 
 Here are some pointers to help you:
   * [Board Product Page](https://www.analog.com/eval-ad4696)
-  * Parts : [16-Bit, 16-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4696)
-            [16-Bit, 16-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4695)
-            [16-Bit, 8-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4697)
-            [16-Bit, 8-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4696)
+  * Parts : [AD4696, 16-Bit, 16-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4696)
+  * Parts : [AD4695, 16-Bit, 16-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4695)
+  * Parts : [AD4697, 16-Bit, 8-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4697)
+  * Parts : [AD4698, 16-Bit, 8-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4698)
   * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad469x
   * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad469x
   * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all

projects/ad469x_fmc/common/ad469x_fmc.txt

@@ -0,0 +1,11 @@
+FMC_pin   FMC_port               Schematic_name     System_top_name        IOSTANDARD  Termination
+
+# ad469x
+
+D8        FMC_LA01_CC_P          SDO                ad469x_spi_sdi         LVCMOS25    #N/A
+D9        FMC_LA01_CC_N          SCK                ad469x_spi_sclk        LVCMOS25    #N/A
+G6        FMC_LA00_CC_P          CS_N               ad469x_spi_cs          LVCMOS25    #N/A
+G7        FMC_LA00_CC_N          CNV_FMC            ad469x_spi_cnv         LVCMOS25    #N/A
+H7        FMC_LA02_P             SDI                ad469x_spi_sdo         LVCMOS25    #N/A
+H10       FMC_LA04_P             RESET              ad469x_resetn          LVCMOS25    #N/A
+H8        FMC_LA02_N             GP0                ad469x_busy_alt_gp0    LVCMOS25    #N/A

projects/ad469x_fmc/zed/system_constr.xdc

@@ -4,14 +4,14 @@
 ###############################################################################
 
 # ad4696_fmc SPI interface
-set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdi]       ; ## D08  FMC_LPC_LA01_CC_P
-set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdo]       ; ## H07  FMC_LPC_LA02_P
-set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sclk]      ; ## D09  FMC_LPC_LA01_CC_N
-set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cs]        ; ## G06  FMC_LPC_LA00_CC_P
-set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cnv]       ; ## G07  FMC_LPC_LA00_CC_N
+set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdi]       ; ## D08  FMC_LA01_CC_P  IO_L14P_T2_SRCC_34
+set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sdo]       ; ## H07  FMC_LA02_P     IO_L20P_T3_34
+set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_sclk]      ; ## D09  FMC_LA01_CC_N  IO_L14N_T2_SRCC_34
+set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cs]        ; ## G06  FMC_LA00_CC_P  IO_L13P_T2_MRCC_34
+set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports ad469x_spi_cnv]       ; ## G07  FMC_LA00_CC_N  IO_L13N_T2_MRCC_34
 
-set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad469x_resetn]        ; ## H10  FMC_LPC_LA04_P
-set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad469x_busy_alt_gp0]  ; ## H08  FMC_LPC_LA02_N
+set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports ad469x_resetn]        ; ## H10  FMC_LA04_P     IO_L15P_T2_DQS_34
+set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports ad469x_busy_alt_gp0]  ; ## H08  FMC_LA02_N     IO_L20N_T3_34
 
 # rename auto-generated clock for SPIEngine to spi_clk - 160MHz
 # NOTE: clk_fpga_0 is the first PL fabric clock, also called $sys_cpu_clk