Skip to content

Commit

Permalink
Update verilog conversion submodule
Browse files Browse the repository at this point in the history
  • Loading branch information
@zhuanhao-wu
zhuanhao-wu committed Jan 10, 2020
1 parent e2115bf commit 7e9be8d
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion tests/data/verilog-conversion
Submodule verilog-conversion updated 4 files
+60 −0 filter/handcrafted/main_sc.mod.v
+20 −0 llnl-examples/handcrafted/sreg.v
+104 −0 llnl-examples/handcrafted/sreg_hdl.txt
+46 −0 llnl-examples/sreg.cpp

0 comments on commit 7e9be8d

Please sign in to comment.