Add AMD PMC/U support

src/data.rs

@@ -10,6 +10,9 @@ cfg_if::cfg_if! {
         pub mod intel_perf_events;
         pub mod intel_icelake_perf_events;
         pub mod intel_sapphire_rapids_perf_events;
+        pub mod amd_perf_events;
+        pub mod amd_genoa_perf_events;
+        pub mod amd_milan_perf_events;
     }
 }
 pub mod interrupts;

src/data/amd_genoa_perf_events.rs

@@ -0,0 +1,24 @@
+use crate::data::perf_stat::{NamedCtr, NamedTypeCtr, PerfType};
+
+static STALL_BACKEND: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Backend-Stalls",
+    config: 0x100001ea0,
+};
+static CYCLES: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Cycles",
+    config: 0x0076,
+};
+
+lazy_static! {
+    pub static ref GENOA_CTRS: Vec<NamedCtr<'static>> = [
+        NamedCtr {
+            name: "stall_backend_pkc",
+            nrs: vec![STALL_BACKEND],
+            drs: vec![CYCLES],
+            scale: 167 //~= 1000/6
+        },
+    ]
+    .to_vec();
+}

src/data/amd_milan_perf_events.rs

@@ -0,0 +1,27 @@
+use crate::data::perf_stat::{NamedCtr, NamedTypeCtr, PerfType};
+
+static STALL_BACKEND_1: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Backend-Stalls-1",
+    config: 0xf7ae,
+};
+static STALL_BACKEND_2: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Backend-Stalls-2",
+    config: 0x27af,
+};
+static CYCLES: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Cycles",
+    config: 0x0076,
+};
+
+lazy_static! {
+    pub static ref MILAN_CTRS: Vec<NamedCtr<'static>> = [NamedCtr {
+        name: "stall_backend_pkc",
+        nrs: vec![STALL_BACKEND_1, STALL_BACKEND_2],
+        drs: vec![CYCLES],
+        scale: 1000
+    }]
+    .to_vec();
+}

src/data/amd_perf_events.rs

@@ -0,0 +1,136 @@
+use crate::data::perf_stat::{NamedCtr, NamedTypeCtr, PerfType};
+
+// amd events
+static INSTRUCTIONS: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Instructions",
+    config: 0x00c0,
+};
+static CYCLES: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Cycles",
+    config: 0x0076,
+};
+static BRANCH_MISPRED: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Branch-Mispredictions",
+    config: 0x00c3,
+};
+static L1_DATA_FILL: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "L1-Data-Fills",
+    config: 0xff44,
+};
+static L1_INSTRUCTION_MISS: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "L1-Instruction-Misses",
+    config: 0x1060,
+};
+static L2_DEMAND_MISS: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "L2-Demand-Misses",
+    config: 0x0964,
+};
+static L1_ANY_FILLS_DRAM: NamedTypeCtr = NamedTypeCtr {
+    // Approximately L3 Misses
+    perf_type: PerfType::RAW,
+    name: "L1-Any-Fills-DRAM",
+    config: 0x0844,
+};
+static STALL_FRONTEND: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Frontend-Stalls",
+    config: 0x00a9,
+};
+static INSTRUCTION_TLB_MISS: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Instruction-TLB-Misses",
+    config: 0x0084,
+};
+static INSTRUCTION_TLB_TW_MISS: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Instruction-TLB-TW-Misses",
+    config: 0x0f85,
+};
+static DATA_TLB_MISS: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Data-TLB-Misses",
+    config: 0xff45,
+};
+static DATA_TLB_TW_MISS: NamedTypeCtr = NamedTypeCtr {
+    perf_type: PerfType::RAW,
+    name: "Data-TLB-TW-Misses",
+    config: 0xf045,
+};
+
+lazy_static! {
+    pub static ref PERF_LIST: Vec<NamedCtr<'static>> = [
+        NamedCtr {
+            name: "ipc",
+            nrs: vec![INSTRUCTIONS],
+            drs: vec![CYCLES],
+            scale: 1
+        },
+        NamedCtr {
+            name: "branch-mpki",
+            nrs: vec![BRANCH_MISPRED],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "data-l1-mpki",
+            nrs: vec![L1_DATA_FILL],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "inst-l1-mpki",
+            nrs: vec![L1_INSTRUCTION_MISS],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "l2-mpki",
+            nrs: vec![L2_DEMAND_MISS],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "l3-mpki",
+            nrs: vec![L1_ANY_FILLS_DRAM],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "stall_frontend_pkc",
+            nrs: vec![STALL_FRONTEND],
+            drs: vec![CYCLES],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "inst-tlb-mpki",
+            nrs: vec![INSTRUCTION_TLB_MISS],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "inst-tlb-tw-mpki",
+            nrs: vec![INSTRUCTION_TLB_TW_MISS],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "data-tlb-mpki",
+            nrs: vec![DATA_TLB_MISS],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+        NamedCtr {
+            name: "data-tlb-tw-pki",
+            nrs: vec![DATA_TLB_TW_MISS],
+            drs: vec![INSTRUCTIONS],
+            scale: 1000
+        },
+    ]
+    .to_vec();
+}

src/data/perf_stat.rs

@@ -17,9 +17,10 @@ use std::sync::Mutex;
 use crate::data::grv_perf_events;
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 use {
-    crate::data::intel_icelake_perf_events::ICX_CTRS, crate::data::intel_perf_events,
-    crate::data::intel_sapphire_rapids_perf_events::SPR_CTRS, crate::data::utils::get_cpu_info,
-    indexmap::IndexMap,
+    crate::data::amd_genoa_perf_events::GENOA_CTRS, crate::data::amd_milan_perf_events::MILAN_CTRS,
+    crate::data::amd_perf_events, crate::data::intel_icelake_perf_events::ICX_CTRS,
+    crate::data::intel_perf_events, crate::data::intel_sapphire_rapids_perf_events::SPR_CTRS,
+    crate::data::utils::get_cpu_info, indexmap::IndexMap,
 };
 
 pub static PERF_STAT_FILE_NAME: &str = "perf_stat";
@@ -140,6 +141,16 @@ impl CollectData for PerfStatRaw {
                         "Intel(R) Xeon(R) Platinum 8488C" => SPR_CTRS.to_vec(),
                         _ => Vec::new(),
                     };
+                } else if cpu_info.vendor == "AuthenticAMD" {
+                    warn!("Event multiplexing may result in bad PMU data."); //TODO: mitigate bad PMU data on AMD instances
+                    perf_list = amd_perf_events::PERF_LIST.to_vec();
+
+                    /* Get Model specific events */
+                    platform_specific_counter = match cpu_info.model_name.get(..13).unwrap_or_default() {
+                        "AMD EPYC 9R14" => GENOA_CTRS.to_vec(),
+                        "AMD EPYC 7R13" => MILAN_CTRS.to_vec(),
+                        _ => Vec::new(),
+                    };
                 } else {
                     return Err(PDError::CollectorPerfUnsupportedCPU.into());
                 }