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RISC-V 64 Port Enabled #594

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merged 4 commits into from
Nov 27, 2024
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Description

This partially enables the installation for RISC-V 64 on Linux systems. This patch can be combined with a new patch to be able to compile and run on RISC-V. The patch removes the dependency to cmake-maven due to unsupported RISC-V architecture.

Once the plugin supports RISC-V, we can drop the external patch.

This patch also includes a new JDK installation for Liberica JDK 21. This JDK includes a port for RISC-V 64.

./bin/tornadovm-installer --jdk liberica-jdk-21 --backend=opencl

Problem description

n. a

Backend/s tested

Mark the backends affected by this PR.

  • OpenCL
  • PTX
  • SPIRV

OS tested

Mark the OS where this PR is tested.

  • Linux
  • OSx
  • Windows

Did you check on FPGAs?

If it is applicable, check your changes on FPGAs.

  • Yes
  • No

How to test the new patch?

On a RISC-V platform:

wget https://gist.githubusercontent.com/jjfumero/c191f7e69a653c4f59f238d5856201aa/raw/d79af888a9873f8a3b44e4cc35a8ae382684cdb2/apply-riscv-patch.sh
bash apply-riscv-patch.sh

Then:

source setvars.sh
Number of Tornado drivers: 1
Driver: OpenCL
  Total number of OpenCL devices  : 1
  Tornado device=0:0  (DEFAULT)
        OPENCL --  [ComputeAorta] -- RefSi G1 RV64
                Global Memory Size: 2.0 GB
                Local Memory Size: 256.0 KB
                Workgroup Dimensions: 3
                Total Number of Block Threads: [1024]
                Max WorkGroup Configuration: [1024, 1024, 1024]
                Device OpenCL C version: OpenCL C 1.2 Clang 19.1.5

Co-authored-by: Thanos Stratikopoulos <34061419+stratika@users.noreply.github.com>
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@stratika stratika left a comment

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Minor updates in documentation. It looks good, I tested Liberica in Linux x86_64.

docs/source/installation.rst Outdated Show resolved Hide resolved
Co-authored-by: Thanos Stratikopoulos <34061419+stratika@users.noreply.github.com>
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@mairooni mairooni left a comment

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LGTM

@jjfumero jjfumero merged commit 17dcba5 into beehive-lab:develop Nov 27, 2024
2 checks passed
@jjfumero jjfumero deleted the feat/port/riscv64 branch November 27, 2024 10:17
jjfumero added a commit to jjfumero/TornadoVM that referenced this pull request Dec 20, 2024
Improvements
=============

- beehive-lab#573: Enhanced output of unit-tests with a summary  of pass-rates and fail-rates.
- beehive-lab#576: Extended support for 3D matrices.
- beehive-lab#580: Extended debug information for execution plans.
- beehive-lab#584: Added helper menu for the ``tornado`` launcher script when no arguments are passed.
- beehive-lab#589: Enable partial loop unrolling for all backends.
- beehive-lab#594: Added RISC-V 64 CPU port support to run OpenCL with vector instructions RVV 1.0 (using the Codeplay OCK Toolkit).
- beehive-lab#598: OpenCL low-level buffers tagged as read, write and read/write based on the data dependency analysis.
- beehive-lab#601: Feature to select an immutable task graph to execute from a multi-task graph execution plan.

Compatibility
=============

- beehive-lab#570:  Extended timeout for all suite of unit-tests.
- beehive-lab#579: Removed legacy JDK 8 and JDK11 build options from the TornadoVM installer.
- beehive-lab#582: Restored tornado runner scripts for IntellIJ.
- beehive-lab#583: Automatic generation of IDE IntelliJ configuration runner files from the TornadoVM command.
- beehive-lab#597: Updated white-list of unit-test and checkstyle improved.

Bug Fixes
=============

- beehive-lab#571: Fix issues with bracket closing for if/loops conditions.
- beehive-lab#572: Fix for printing default execution plans (execution plans with default parameters).
- beehive-lab#575: Fix the Level Zero version used for building the SPIR-V backend.
- beehive-lab#577: Fix checkstyle.
- beehive-lab#587: Fix thread scheduler for new NVIDIA Drivers.
- beehive-lab#592: Fix ``Float.POSITIVE_INFINITY`` and ``Float.NEGATIVE_INFINITIVE`` constants for the OpenCL, CUDA and SPIR-V backends.
- beehive-lab#596: Fix extra closing bracket during the code-generation for the FPGAs.
- Remove the intermediate CUDA pinned memory regions in the JNI code: [link](beehive-lab@9c3f8ce)
- Fix bitwise negation operations for the PTX backend:  [link](beehive-lab@0db1cd3)
- `GetBackendImpl::getAllDevices` thread-safe: [link](beehive-lab@0d44252)
- Check size elements for memory segments: [link](beehive-lab@4360385)
@jjfumero jjfumero mentioned this pull request Dec 20, 2024
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4 participants