Code

add riscv64 backend for cranelift.#4271

Code

Merged

cfallin merged 208 commits intobytecodealliance:mainbytecodealliance/wasmtime:mainfrom yuyang-ok:risc-vyuyang-ok/wasmtime:risc-vCopy head branch name to clipboardSep 28, 2022

+21,024-36

Commits

Commits on Apr 26, 2022

• risc-v hello_work works

  756445638

  committed
  a638a87

• virtual sp ajust

  756445638

  committed
  4a2c69f

• better print for Amode

  756445638

  committed
  ee7225e

• wired..

  756445638

  committed
  c7dc9b8

Commits on Apr 27, 2022

• float compare

  756445638

  committed
  62e74ae

• atomic operations and op_name

  756445638

  committed
  60a44a1

• commit for save now.

  756445638

  committed
  53a3915

Commits on Apr 28, 2022

• name upper snake case to camel case

  756445638

  committed
  90690c3

• float compare and refactor int compare and ...

  756445638

  committed
  a4dbc28

• some regclass error

  756445638

  committed
  1c7c644

Commits on Apr 29, 2022

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  1592896

• simple atomic operation

  756445638

  committed
  ff0af05

• Merge branch 'risc-v' of https://github.com/yuyang-ok/wasmtime into risc-v

  756445638

  committed
  d1837ed

Commits on Apr 30, 2022

• keep up with upstream

  756445638

  committed
  fb9a098

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  018448b

• save prologue register error and abi

  756445638

  committed
  acdd022

• load and store

  756445638

  committed
  1fe486d

• test_riscv64_binemit and abi is wried

  756445638

  committed
  075fc04

• abi reference outdated paper

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  committed
  61ef4f0

Commits on May 1, 2022

• atomic load and store

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  committed
  6490e28

• Jump -> Jal

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  committed
  03d5b18

• you cannot know patch size at lower stage,so BranchTarge::Patch is always a bug

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  committed
  e47480c

Commits on May 3, 2022

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  3679f94

• reg alloc not working but I need merge upstream

  756445638

  committed
  2dcd48a

• Merge branch 'risc-v' of https://github.com/yuyang-ok/wasmtime into risc-v

  756445638

  committed
  1252292

Commits on May 4, 2022

• use alloc consumer correctly

  756445638

  committed
  fac524c

• missing bind label

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  committed
  a89e43e

Commits on May 5, 2022

• lower select

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  committed
  8b3705c

• lower is_null

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  committed
  c5b12b8

• i128 compare

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  committed
  f6fc47d

Commits on May 6, 2022

• brtable

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  committed
  8c730fb

• emit test

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  committed
  5c0f12c

• emit_test forget fcsr operations

  756445638

  committed
  ba132f6

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  a09120d

• jalr12 is not a labeluse

  756445638

  committed
  e246e89

Commits on May 7, 2022

• atomic cas and atomic sub

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  committed
  5ffa538

Commits on May 8, 2022

• extend integer and bool value

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  committed
  c87312c

• lower insts

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  committed
  d0cc8e9

• imax ,imin ... and fadd

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  committed
  2af34ca

• float binary op generate moved different palce

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  committed
  1247e91

• risc_v rename to riscv64

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  committed
  289ac35

• branch offset should contains itself

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  committed
  ccd2347

Commits on May 9, 2022

• Update main.yml

  yuyang-ok

  authored
  554ef78

• callind

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  committed
  1b17f30

• Merge branch 'risc-v' of https://github.com/yuyang-ok/wasmtime into risc-v

  756445638

  committed
  0b642eb

Commits on May 10, 2022

• gen callind,look like caller save register not save,figure it out.

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  committed
  0842513

Commits on May 11, 2022

• explicitly save ra register.

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  committed
  fe2d9a8

• lower load_addr

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  committed
  5df6e49

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  5429858

Commits on May 12, 2022

• atomic cas test on my qemu emulator

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  committed
  2dcdb34

• pass test arithmetic.clif on my local machine.

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  committed
  f03b082

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  7e90d80

Commits on May 13, 2022

• generate bool const and band

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  committed
  8240808

• Merge branch 'risc-v' of https://github.com/yuyang-ok/wasmtime into risc-v

  756445638

  committed
  3fc2560

Commits on May 14, 2022

• i128 add implemented

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  committed
  de1b428

• i12b sub implemented.

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  committed
  4a0db0d

Commits on May 15, 2022

• compute_abi_loc should in params order

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  committed
  142ca99

Commits on May 16, 2022

• read and write csrs

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  committed
  c825028

Commits on May 17, 2022

• add bitmanip instructions

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  committed
  736eb21

• I need mrege upstream

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  committed
  92f9d49

• emit test for bitmanip

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  committed
  e77a395

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  cf687eb

Commits on May 18, 2022

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  0466b9b

• keep up with upstream

  yuyang-ok

  committed
  a8ca031

• Merge branch 'risc-v' of https://github.com/yuyang-ok/wasmtime into risc-v

  yuyang-ok

  committed
  df3173b

Commits on May 19, 2022

• compute args location

  yuyang-ok

  committed
  5147f7d

Commits on May 20, 2022

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  83aa914

• brbr_table

  yuyang-ok

  committed
  89e8f32

• uextend

  yuyang-ok

  committed
  1985271

• modify the design of funct12

  yuyang-ok

  committed
  a3a44a0

Commits on May 21, 2022

• implemente band_not

  yuyang-ok

  committed
  386a5d4

• lower icmp and popcnt

  yuyang-ok

  committed
  bf222c5

Commits on May 22, 2022

• lower float compare

  yuyang-ok

  committed
  d18f4f6

• mul high part

  yuyang-ok

  committed
  281173c

• lower rotl and rotr

  yuyang-ok

  committed
  2276e3c

• lower i128 compare

  yuyang-ok

  committed
  11c0599

Commits on May 23, 2022

• riscv64 add first pricise-output test

  yuyang-ok

  committed
  0eceee5

Commits on May 24, 2022

• lower cls

  yuyang-ok

  committed
  c8df735

• lower ctz

  yuyang-ok

  committed
  f85c4c3

• lower i128 xnor

  yuyang-ok

  committed
  8b9bf6e

Commits on May 25, 2022

• lower bits rotation.

  yuyang-ok

  committed
  0443019

• remove function patch_taken_list.

  yuyang-ok

  committed
  e90472b

Commits on May 26, 2022

• lower float operations

  yuyang-ok

  committed
  2887e37

• fcvt_int_sat missing save fcsr

  yuyang-ok

  committed
  0c3df39

Commits on May 27, 2022

• lower call

  yuyang-ok

  committed
  9dbc1b3

Commits on May 28, 2022

• lower instruction and add some test

  yuyang-ok

  committed
  1314026

Commits on May 30, 2022

• implement bitrev.

  yuyang-ok

  committed
  047c188

Commits on Jun 2, 2022

• look up architecture for riscv64

  yuyang-ok

  committed
  a295c76

• lower cls

  yuyang-ok

  committed
  c3b7aae

• lower i128 sshr.

  yuyang-ok

  committed
  0833064

Commits on Jun 3, 2022

• lowering instructions.

  yuyang-ok

  committed
  b38375a

• lowring and do some testing.

  yuyang-ok

  committed
  7ae0a77

Commits on Jun 4, 2022

• emit island for brtable emit and caculate worst instruction size.

  yuyang-ok

  committed
  df86448

• move some code.

  yuyang-ok

  committed
  da1b55d

• using float rounding mode in instruction instead of fcsr.

  yuyang-ok

  committed
  38bad2e

• divide integer operation and float operation instruction.

  yuyang-ok

  committed
  8e82985

Commits on Jun 5, 2022

• emit call.

  yuyang-ok

  committed
  bf4f94c

• lowering instrctions and maybe better naming.

  yuyang-ok

  committed
  93e9e43

Commits on Jun 7, 2022

• riscv64 mod test.

  yuyang-ok

  committed
  5d7f4ab

• remove static TRIPLE

  yuyang-ok

  committed
  006d1ae

• add precise-output test.

  yuyang-ok

  committed
  2e17b2d

• format uextend and sextend.

  yuyang-ok

  committed
  350211a

• generate settings for riscv64gc

  yuyang-ok

  committed
  d525770

Commits on Jun 8, 2022

• test target shoule be riscv64gc.

  yuyang-ok

  committed
  a4e94f3

Commits on Jun 9, 2022

• add some test for float.

  yuyang-ok

  committed
  506db09

Commits on Jun 10, 2022

• add all float test for riscv64.

  yuyang-ok

  committed
  6c9cac3

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  b0a3ac4

Commits on Jun 11, 2022

• fix load constant bug.

  yuyang-ok

  committed
  6af7fb1

Commits on Jun 12, 2022

• atomic operations.

  yuyang-ok

  committed
  b1ab139

Commits on Jun 13, 2022

• pass all runtests.

  yuyang-ok

  committed
  18fd653

Commits on Jun 14, 2022

• handle immediates.

  yuyang-ok

  committed
  aa6fcd2

• some tests.

  yuyang-ok

  committed
  50d627e

Commits on Jun 15, 2022

• Update main.yml

  yuyang-ok

  authored
  fd3ce1a

Commits on Jun 16, 2022

• fix LableUse max range error.

  yuyang-ok

  committed
  68f1c80

• Merge branch 'risc-v' of https://github.com/yuyang-ok/wasmtime into risc-v

  yuyang-ok

  committed
  851354c

• construct_auipc_and_jalr should use generate_imm and some better coding.

  yuyang-ok

  committed
  bd31fda

• reimplemented floatnot equal compare and float compare args.

  yuyang-ok

  committed
  788290e

• float to int representation should use little endian.

  yuyang-ok

  committed
  3cce489

Commits on Jun 17, 2022

• comment in assembly should using '##' instead of ';;'.

  yuyang-ok

  committed
  d154b77

Commits on Jun 18, 2022

• modify the way to construct AluRRImm12.

  yuyang-ok

  committed
  da37a7a

• aluRRImm12 emiting.

  yuyang-ok

  committed
  67c0d55

Commits on Jun 23, 2022

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  570c88b

Commits on Jun 24, 2022

• lower atomic rmw using ISLE.

  yuyang-ok

  committed
  c9e487c

• rewrite float lowering using ISLE.

  yuyang-ok

  committed
  fa409ba

• rewrite some handwritten code to ISLE.

  yuyang-ok

  committed
  c31e977

Commits on Jun 26, 2022

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  f2109d3

• continue to rewritting handwritten code to ISLE.

  yuyang-ok

  committed
  48592cc

• rewrite load store and fcmp to ISLE.

  yuyang-ok

  committed
  32c93d1

Commits on Jun 27, 2022

• rewrite float convert and symbol_value ... to ISLE.

  yuyang-ok

  committed
  80c5ec4

• rewrite clz and i128 add ... to ISLE.

  yuyang-ok

  committed
  e922f95

Commits on Jun 28, 2022

• remote cls umlhi and ... to ISLE.

  yuyang-ok

  committed
  933a5af

• remove parameter Type for alu_rrr.

  yuyang-ok

  committed
  4745f9c

• rewite i128 rorate to ISLE.

  yuyang-ok

  committed
  b9868ed

• lower i128 rotate remove shamt127.

  yuyang-ok

  committed
  b07a99e

• reimplemented cls.

  yuyang-ok

  committed
  25d6ade

• Merge branch 'main' of https://github.com/bytecodealliance/wasmtime into risc-v

  yuyang-ok

  committed
  3093d1c

• rewrite i128 shifts to ISLE.

  yuyang-ok

  committed
  02c8876

Commits on Jun 29, 2022

• remove term ty_unused_bits_neg.

  yuyang-ok

  committed
  8bca3d2

Commits on Jul 2, 2022

• rewrite selectif trapif... to ISLE.

  yuyang-ok

  committed
  65f0e43

Commits on Jul 4, 2022

• float binary op should move to x and atomic_store.

  yuyang-ok

  committed
  f26d2db

Commits on Jul 6, 2022

• reimplemet atomic load store cas ...

  yuyang-ok

  committed
  e599fd7

• better sextend.

  yuyang-ok

  committed
  117df88

• save ra register at gen_prologue_frame_setup.

  yuyang-ok

  committed
  8e88517

Commits on Jul 7, 2022

• lowering integer compare.

  yuyang-ok

  committed
  eb8dc89

• remove gcc tool chain in emit_test.rs.

  yuyang-ok

  committed
  4c0a8f3

• save return address using wrong stack offset.

  yuyang-ok

  committed
  7cef970

Commits on Jul 8, 2022

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  ac2219a

Commits on Jul 11, 2022

• add unwindinfo for riscv64.

  yuyang-ok

  committed
  027bfe2

• fabs implemetation and run tests.

  yuyang-ok

  committed
  c8b2142

Commits on Jul 13, 2022

• emiting nearest ceil ....

  yuyang-ok

  committed
  67962f7

• rename riscv64gc to riscv64

  yuyang-ok

  committed
  03f377d

Commits on Jul 14, 2022

• fmax-pseudo implement in riscv64 and code tidy.

  yuyang-ok

  committed
  6e6da4d

• missing meta file for riscv64.

  yuyang-ok

  committed
  05b31d6

Commits on Jul 16, 2022

• remove function param_or_rets_xregs.

  yuyang-ok

  committed
  ed14d45

• Update run_command.rs

  yuyang-ok

  authored
  bf5d0ad

Commits on Jul 21, 2022

• add test fadd ... on riscv64.

  yuyang-ok

  committed
  64a03c7

Commits on Jul 23, 2022

• riscv64 merge upstream.

  yuyang-ok

  committed
  485b982

Commits on Jul 25, 2022

• Merge branch 'risc-v' of https://github.com/yuyang-ok/wasmtime into risc-v

  yuyang-ok

  committed
  c05c82d

• emit libcall.

  yuyang-ok

  committed
  0487b9d

Commits on Aug 2, 2022

• port fiber to riscv64 but unwind not working.

  yuyang-ok

  committed
  ddda7c6

Commits on Aug 7, 2022

• fix riscv64 fiber cfi directives.

  yuyang-ok

  committed
  1184370

Commits on Aug 8, 2022

• keep up with upstream.

  yuyang-ok

  committed
  cd86265

• Update main.yml

  yuyang-ok

  authored
  2c0f434

Commits on Aug 10, 2022

• code tidy.

  yuyang-ok

  committed
  ecfba31

• port riscv64 trampolines traphandlers ...

  yuyang-ok

  committed
  283753d

Commits on Aug 11, 2022

• gen probe_stack and int_zero_reg can take bool type.

  yuyang-ok

  committed
  6a1de05

Commits on Aug 13, 2022

• riscv reloc and dwarf register mapping.

  yuyang-ok

  committed
  5cbaa01

Commits on Aug 16, 2022

• implemented popcnt when extension B are absent and setup frame ...

  yuyang-ok

  committed
  5f66faf

Commits on Aug 17, 2022

• implemented rev8... when b extension is missing.

  yuyang-ok

  committed
  1dbfb79

• remodel call convertion from x86_64.

  yuyang-ok

  committed
  1260b00

Commits on Aug 18, 2022

• wasmtime_system_v only use one register to store result.

  yuyang-ok

  committed
  bf03d8a

• riscv64 wasmtime abi only one value can in a register.

  yuyang-ok

  committed
  19ef4a6

• add HeapOutOfBounds for memory operation.

  yuyang-ok

  committed
  dee6661

• re-implemented rev8 using loop.

  yuyang-ok

  committed
  cfb3371

Commits on Aug 19, 2022

• Merge branch 'main' of https://github.com/bytecodealliance/wasmtime into risc-v

  yuyang-ok

  committed
  3ab74a5

Commits on Aug 21, 2022

• Merge branch 'main' of https://github.com/bytecodealliance/wasmtime into risc-v

  yuyang-ok

  committed
  78a1bc6

Commits on Aug 23, 2022

• riscv support atomic i8 and i16.

  yuyang-ok

  committed
  34477cf

Commits on Aug 24, 2022

• Merge branch 'main' of https://github.com/bytecodealliance/wasmtime into risc-v

  yuyang-ok

  committed
  8c5b50f

Commits on Aug 25, 2022

• float convert to int overflow and div by zero exceptions.

  yuyang-ok

  committed
  940d5ea

Commits on Aug 26, 2022

• fix br_table.

  yuyang-ok

  committed
  f0d5235

Commits on Aug 29, 2022

• move i32 to f32 register use fmv.w.x instead of fmx.d.x.

  yuyang-ok

  committed
  0de2cd5

Commits on Aug 31, 2022

• gen divide by zero trap at ISLE.

  yuyang-ok

  committed
  0dc632f

• Merge branch 'bytecodealliance:main' into risc-v

  yuyang-ok

  authored
  b0d4930

Commits on Sep 13, 2022

• Fix some errors, and disable SIMD tests on rv64gc.

  cfallin

  committed
  5cf133b

• Merge remote-tracking branch 'upstream/main' into risc-v

  cfallin

  committed
  ec084de

• Test updates.

  cfallin

  committed
  12316b8

• cargo-fmt.

  cfallin

  committed
  07e90ba

• Miscellaneous fixups.

  cfallin

  committed
  28e2d8f

• cargo-fmt.

  cfallin

  committed
  dc8b7ee

Commits on Sep 14, 2022

• add inline_probe_stack and remove some extractor for ISLE.

  yuyang-ok

  committed
  73c7096

• load_ra base on if preserve_frame_pointers.

  yuyang-ok

  committed
  924f67f

Commits on Sep 15, 2022

• uadd_overflow add i8... and add for i128.

  yuyang-ok

  committed
  b51a998

• Run CI on all branches

  afonso360

  committed
  9f283ef

• Add riscv64 builds

  afonso360

  committed
  e3f5de3

• cranelift: Cleanup warning

  afonso360

  committed
  d3ef08b

Commits on Sep 16, 2022

• Merge branch 'main' of https://github.com/bytecodealliance/wasmtime into risc-v

  yuyang-ok

  committed
  eb7148a

Commits on Sep 20, 2022

• Merge branch 'risc-v' of https://github.com/afonso360/wasmtime into risc-v

  yuyang-ok

  committed
  5887d57

Commits on Sep 21, 2022

• disable host_segfault async pooling-alloctor test.

  yuyang-ok

  committed
  995a695

• Merge branch 'main' of https://github.com/bytecodealliance/wasmtime into risc-v

  yuyang-ok

  committed
  16b1b19

Commits on Sep 22, 2022

• fix accidently remove test target for urem.clif.

  yuyang-ok

  committed
  862c9ad

• Merge branch 'main' of https://github.com/bytecodealliance/wasmtime into risc-v

  yuyang-ok

  committed
  e48549a

Commits on Sep 23, 2022

• fix gen_call and gen_memcpy.

  yuyang-ok

  committed
  822ebd5

• fix riscv64 test compiler-output.

  yuyang-ok

  committed
  b20499a

• fix test_isa_flags_mismatch test failed on riscv64.

  yuyang-ok

  committed
  5463532

• fix test_isa_flags_mismatch test failed on riscv64.

  yuyang-ok

  committed
  75ef742

Commits on Sep 25, 2022

• Merge branch 'main' of https://github.com/bytecodealliance/wasmtime into risc-v

  yuyang-ok

  committed
  e71d655

• fix ISLE formatting.

  yuyang-ok

  committed
  0aa33c1

Commits on Sep 27, 2022

• fix is_isa_compatible for riscv64.

  yuyang-ok

  committed
  96ef1e7