add riscv64 backend for cranelift. #4271

yuyang-ok · 2022-06-15T05:58:45Z

I am been trying to add riscv64 backend for cranelift these days.
right now I have pass all run test in filetests.

some features not implemented right now.
i128 mul div rem, all simd type and compare overflow.

some test need platform support.
like bitrev need qemu-riscv64 support bitmanip and zbkb extension (don't know how to enable it.).

…isc-v

…ways a bug

…isc-v

…nto risc-v

yuyang-ok · 2022-09-25T02:34:23Z

@cfallin I think we are ready.
maybe some part not appropriate like https://github.com/yuyang-ok/wasmtime/blob/risc-v/crates/wasmtime/src/engine.rs#L493 .
maybe you can help me a little??

a1phyr · 2022-09-26T07:58:44Z

I think you could do the same that for s390x, i.e. calling getauxval by yourself.

You can find a RISC-V example in std_detect (the implementation of is_riscv64_feature_detected!) here.

cranelift/native/Cargo.toml

yuyang-ok · 2022-09-26T10:50:07Z

I think you could do the same that for s390x, i.e. calling getauxval by yourself.

still look a little hard to use to me. look like need use C???

yuyang-ok · 2022-09-26T11:10:10Z

@cfallin what do you think appropriate to solve is_riscv64_feature_detected???

cfallin · 2022-09-27T22:05:10Z

@cfallin what do you think appropriate to solve is_riscv64_feature_detected???

If we want to wait for stabilization of the feature-detection macro in the standard library, I don't see anything wrong with assuming a baseline RISC-V ISA level for now (in other words, running with no features ever detected). Does this seem reasonable or would it result in important optimizations going missing?

cfallin

@yuyang-ok -- I went over the rest of the code and I think this looks generally fine. At least, passing all Wasm core tests indicates that this is of sufficient quality to merge, and can be refined and improved more in-tree.

I do have one minor comment below; and there's my answer to the getauxval question above. I'm not opposed to ignoring the getauxval issue for now (and simply not detecting features), if baseline RISC-V without extra ISA features is good enough to get started. And re: the below, a comment and factoring out the logic to a helper should be enough I think. Let me know once you've done this and then we can merge.

Thanks so much for the patience and hard work as we've reviewed this; I'm really excited to see it merge soon!

cranelift/filetests/src/test_run.rs

yuyang-ok · 2022-09-27T22:59:58Z

Does this seem reasonable or would it result in important optimizations going missing?

popcnt,ctz,rev8,brev8 will fallback to loop implementation, seen reasonable to me, I think these instructions are used rare to me.

cfallin

Updates look good to me -- thanks!

I'm going to go ahead and merge this now. Thanks again @yuyang-ok -- this was a huge amount of work.

More improvements are always welcome of course, from you and others -- anyone who wants to talk about further improvements to the RISC-V backend, please feel free to join our project meeting or file issues!

yuyang-ok · 2022-09-28T00:34:15Z

@cfallin ok,thanks. :-)

Our submodule was accidentally reverted to an older commit as part of bytecodealliance#4271 and while it could be updated to as it was before I went ahead and updated it to `main`.

* Update spec test repo Our submodule was accidentally reverted to an older commit as part of #4271 and while it could be updated to as it was before I went ahead and updated it to `main`. * Update ignore directives and test multi-memory * Update riscv ignores

rice7th · 2022-10-08T15:04:21Z

@cfallin ok,thanks. :-)

Congratulations!

martasp · 2022-11-12T13:02:38Z

How can I use this feature, is there documentation?
How can I set a target risc5 and produce Linux risc5 elf binary?
I would want to use it like that:

wasmtime exampleProgram.wasm --target risc5

archanox · 2022-11-12T15:48:26Z

This work is for RISC-V not risc5.
You'll likely need to use riscv64gc as per the changes in this PR.

martasp · 2022-11-12T16:40:45Z

I see that we have binaries riscv64gc here: https://github.com/bytecodealliance/wasmtime/releases/tag/v2.0.2 therefore It should probably work on riscv64 Linux. So I tried to install wasmtime in riscv64 Linux but without success.
Probably there is a difference between riscv64 and riscv64gc but I'm kinda new to these things, where can I learn it, any good resources?

[root@localhost ~]# curl https://wasmtime.dev/install.sh -sSf | bash
Error: Sorry! Wasmtime currently only provides pre-built binaries for x86_64 (Linux, macOS, Windows), aa
rch64 (Linux, macOS), and s390x (Linux).
 
[root@localhost ~]# uname
Linux
[root@localhost ~]# uname -p
riscv64

bjorn3 · 2022-11-12T16:48:11Z

The script at https://wasmtime.dev/install.sh hasn't been updated yet for riscv64 support. You should probably directly download the binary from https://github.com/bytecodealliance/wasmtime/releases/tag/v2.0.2.

756445638 and others added 30 commits April 26, 2022 08:11

risc-v hello_work works

a638a87

virtual sp ajust

4a2c69f

better print for Amode

ee7225e

wired..

c7dc9b8

float compare

62e74ae

atomic operations and op_name

60a44a1

commit for save now.

53a3915

name upper snake case to camel case

90690c3

float compare and refactor int compare and ...

a4dbc28

some regclass error

1c7c644

Merge branch 'bytecodealliance:main' into risc-v

1592896

simple atomic operation

ff0af05

Merge branch 'risc-v' of https://github.com/yuyang-ok/wasmtime into r…

d1837ed

…isc-v

keep up with upstream

fb9a098

Merge branch 'bytecodealliance:main' into risc-v

018448b

save prologue register error and abi

acdd022

load and store

1fe486d

test_riscv64_binemit and abi is wried

075fc04

abi reference outdated paper

61ef4f0

atomic load and store

6490e28

Jump -> Jal

03d5b18

you cannot know patch size at lower stage,so BranchTarge::Patch is al…

e47480c

…ways a bug

Merge branch 'bytecodealliance:main' into risc-v

3679f94

reg alloc not working but I need merge upstream

2dcd48a

Merge branch 'risc-v' of https://github.com/yuyang-ok/wasmtime into r…

1252292

…isc-v

use alloc consumer correctly

fac524c

missing bind label

a89e43e

lower select

8b3705c

lower is_null

c5b12b8

i128 compare

f6fc47d

yuyang-ok added 6 commits September 23, 2022 09:57

fix gen_call and gen_memcpy.

822ebd5

fix riscv64 test compiler-output.

b20499a

fix test_isa_flags_mismatch test failed on riscv64.

5463532

fix test_isa_flags_mismatch test failed on riscv64.

75ef742

Merge branch 'main' of https://github.com/bytecodealliance/wasmtime i…

e71d655

…nto risc-v

fix ISLE formatting.

0aa33c1

afonso360 reviewed Sep 26, 2022

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cranelift/native/Cargo.toml Outdated Show resolved Hide resolved

cfallin approved these changes Sep 27, 2022

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cranelift/filetests/src/test_run.rs Outdated Show resolved Hide resolved

fix is_isa_compatible for riscv64.

96ef1e7

cfallin approved these changes Sep 28, 2022

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cfallin merged commit cdecc85 into bytecodealliance:main Sep 28, 2022

alexcrichton mentioned this pull request Sep 28, 2022

Update spec test repo #4974

Merged

a1phyr mentioned this pull request Sep 29, 2022

RISC-V support dotnet/runtime#36748

Open

sanxiyn mentioned this pull request Sep 29, 2022

Support RISC-V target in new backend framework #2217

Closed

syrusakbary mentioned this pull request Oct 21, 2022

Feat riscv llvm and cranelift wasmerio/wasmer#3244

Merged

cfallin mentioned this pull request Jul 5, 2023

Make wasmtime-cranelift::Builder public #6681

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add riscv64 backend for cranelift. #4271

add riscv64 backend for cranelift. #4271

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bjorn3 commented Nov 12, 2022

add riscv64 backend for cranelift. #4271

add riscv64 backend for cranelift. #4271

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