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add riscv64 backend for cranelift. #4271
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,25 @@ | ||
use crate::cdsl::isa::TargetIsa; | ||
use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder}; | ||
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use crate::shared::Definitions as SharedDefinitions; | ||
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fn define_settings(_shared: &SettingGroup) -> SettingGroup { | ||
let mut setting = SettingGroupBuilder::new("riscv64gc"); | ||
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setting.add_bool("has_extension_m", "has extension M?", "", false); | ||
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setting.add_bool("has_extension_a", "has extension A?", "", false); | ||
setting.add_bool("has_extension_f", "has extension F?", "", false); | ||
setting.add_bool("has_extension_d", "has extension D?", "", false); | ||
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setting.add_bool("has_extension_v", "has extension V?", "", false); | ||
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setting.add_bool("has_extension_b", "has extension B?", "", false); | ||
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setting.add_bool("has_extension_zbkb", "has extension zbkb?", "", false); | ||
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setting.build() | ||
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} | ||
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pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa { | ||
let settings = define_settings(&shared_defs.settings); | ||
TargetIsa::new("riscv64gc", settings) | ||
} |
Original file line number | Diff line number | Diff line change |
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@@ -59,6 +59,13 @@ pub enum Reloc { | |
/// Set the add immediate field to the low 12 bits of the final address. Does not check for overflow. | ||
/// This is equivalent to `R_AARCH64_TLSGD_ADD_LO12_NC` in the [aaelf64](https://github.com/ARM-software/abi-aa/blob/2bcab1e3b22d55170c563c3c7940134089176746/aaelf64/aaelf64.rst#relocations-for-thread-local-storage) | ||
Aarch64TlsGdAddLo12Nc, | ||
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/// procedure call. | ||
/// call symbol | ||
/// expands to the following assembly and relocation: | ||
/// auipc ra, 0 | ||
/// jalr ra, ra, 0 | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. Can you say what ELF relocation kind this is equivalent to? There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. not very clear, I found it in riscv-abi.pdf There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more.
@cfallin I not quit understand the question. |
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RiscvCall, | ||
} | ||
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impl fmt::Display for Reloc { | ||
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@@ -74,11 +81,11 @@ impl fmt::Display for Reloc { | |
Self::X86CallPLTRel4 => write!(f, "CallPLTRel4"), | ||
Self::X86GOTPCRel4 => write!(f, "GOTPCRel4"), | ||
Self::Arm32Call | Self::Arm64Call => write!(f, "Call"), | ||
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Self::ElfX86_64TlsGd => write!(f, "ElfX86_64TlsGd"), | ||
Self::MachOX86_64Tlv => write!(f, "MachOX86_64Tlv"), | ||
Self::Aarch64TlsGdAdrPage21 => write!(f, "Aarch64TlsGdAdrPage21"), | ||
Self::Aarch64TlsGdAddLo12Nc => write!(f, "Aarch64TlsGdAddLo12Nc"), | ||
Self::RiscvCall => write!(f, "riscvCall"), | ||
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} | ||
} | ||
} | ||
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nit:
to keep visual separation.
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Also I think it should be called
riscv64i
orrv64i
instead. This is the name of the base profile. It should be possible to enable and disable the extensions that form ricv64gc without requiring a completely new backend.