add riscv64 backend for cranelift.

.github/workflows/main.yml

@@ -233,6 +233,12 @@ jobs:
             gcc: s390x-linux-gnu-gcc
             qemu: qemu-s390x -L /usr/s390x-linux-gnu
             qemu_target: s390x-linux-user
+          - os: ubuntu-latest
+            target: riscv64gc-unknown-linux-gnu
+            gcc_package: gcc-riscv64-linux-gnu
+            gcc: riscv64-linux-gnu-gcc
+            qemu: qemu-riscv64 -L /usr/riscv64-linux-gnu
+            qemu_target: riscv64-linux-user
     steps:
     - uses: actions/checkout@v2
       with:
@@ -404,6 +410,9 @@ jobs:
         - build: s390x-linux
           os: ubuntu-latest
           target: s390x-unknown-linux-gnu
+        - build: riscv64gc-linux
+          os: ubuntu-latest
+          target: riscv64gc-unknown-linux-gnu
     steps:
     - uses: actions/checkout@v2
       with:

build.rs

@@ -172,6 +172,9 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
             // FIXME: These tests fail under qemu due to a qemu bug.
             (_, "simd_f32x4_pmin_pmax") if platform_is_s390x() => return true,
             (_, "simd_f64x2_pmin_pmax") if platform_is_s390x() => return true,
+            // riscv64 backend does not yet have a fully complete SIMD backend.
+            ("simd", _) if platform_is_riscv64() => return true,
+            ("memory64", "simd") if platform_is_riscv64() => return true,
             _ => {}
         },
         _ => panic!("unrecognized strategy"),
@@ -183,3 +186,7 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
 fn platform_is_s390x() -> bool {
     env::var("CARGO_CFG_TARGET_ARCH").unwrap() == "s390x"
 }
+
+fn platform_is_riscv64() -> bool {
+    env::var("CARGO_CFG_TARGET_ARCH").unwrap() == "riscv64"
+}

ci/docker/riscv64gc-linux/Dockerfile

@@ -0,0 +1,7 @@
+FROM ubuntu:22.04
+
+RUN apt-get update -y && apt-get install -y gcc gcc-riscv64-linux-gnu ca-certificates
+
+ENV PATH=$PATH:/rust/bin
+ENV CARGO_BUILD_TARGET=riscv64gc-unknown-linux-gnu
+ENV CARGO_TARGET_RISCV64GC_UNKNOWN_LINUX_GNU_LINKER=riscv64-linux-gnu-gcc

cranelift/codegen/Cargo.toml

@@ -68,7 +68,7 @@ unwind = ["gimli"]
 x86 = []
 arm64 = []
 s390x = []
-
+riscv64 = []
 # Stub feature that does nothing, for Cargo-features compatibility: the new
 # backend is the default now.
 experimental_x64 = []
@@ -77,7 +77,8 @@ experimental_x64 = []
 all-arch = [
     "x86",
     "arm64",
-    "s390x"
+    "s390x",
+    "riscv64"
 ]
 
 # For dependent crates that want to serialize some parts of cranelift

cranelift/codegen/build.rs

@@ -187,6 +187,8 @@ fn get_isle_compilations(
     let src_isa_s390x =
         make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("isa").join("s390x"));
 
+    let src_isa_risc_v =
+        make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("isa").join("riscv64"));
     // This is a set of ISLE compilation units.
     //
     // The format of each entry is:
@@ -234,6 +236,16 @@ fn get_isle_compilations(
                 ],
                 untracked_inputs: vec![clif_isle.clone()],
             },
+            // The risc-v instruction selector.
+            IsleCompilation {
+                output: out_dir.join("isle_riscv64.rs"),
+                inputs: vec![
+                    prelude_isle.clone(),
+                    src_isa_risc_v.join("inst.isle"),
+                    src_isa_risc_v.join("lower.isle"),
+                ],
+                untracked_inputs: vec![clif_isle.clone()],
+            },
         ],
     })
 }

cranelift/codegen/meta/src/isa/mod.rs

@@ -4,6 +4,7 @@ use crate::shared::Definitions as SharedDefinitions;
 use std::fmt;
 
 mod arm64;
+mod riscv64;
 mod s390x;
 pub(crate) mod x86;
 
@@ -13,6 +14,7 @@ pub enum Isa {
     X86,
     Arm64,
     S390x,
+    Riscv64,
 }
 
 impl Isa {
@@ -30,13 +32,14 @@ impl Isa {
             "aarch64" => Some(Isa::Arm64),
             "s390x" => Some(Isa::S390x),
             x if ["x86_64", "i386", "i586", "i686"].contains(&x) => Some(Isa::X86),
+            "riscv64" | "riscv64gc" | "riscv64imac" => Some(Isa::Riscv64),
             _ => None,
         }
     }
 
     /// Returns all supported isa targets.
     pub fn all() -> &'static [Isa] {
-        &[Isa::X86, Isa::Arm64, Isa::S390x]
+        &[Isa::X86, Isa::Arm64, Isa::S390x, Isa::Riscv64]
     }
 }
 
@@ -47,6 +50,7 @@ impl fmt::Display for Isa {
             Isa::X86 => write!(f, "x86"),
             Isa::Arm64 => write!(f, "arm64"),
             Isa::S390x => write!(f, "s390x"),
+            Isa::Riscv64 => write!(f, "riscv64"),
         }
     }
 }
@@ -57,6 +61,7 @@ pub(crate) fn define(isas: &[Isa], shared_defs: &mut SharedDefinitions) -> Vec<T
             Isa::X86 => x86::define(shared_defs),
             Isa::Arm64 => arm64::define(shared_defs),
             Isa::S390x => s390x::define(shared_defs),
+            Isa::Riscv64 => riscv64::define(shared_defs),
         })
         .collect()
 }

cranelift/codegen/meta/src/isa/riscv64.rs

@@ -0,0 +1,27 @@
+use crate::cdsl::isa::TargetIsa;
+use crate::cdsl::settings::{SettingGroup, SettingGroupBuilder};
+
+use crate::shared::Definitions as SharedDefinitions;
+
+fn define_settings(_shared: &SettingGroup) -> SettingGroup {
+    let mut setting = SettingGroupBuilder::new("riscv64");
+
+    let _has_m = setting.add_bool("has_m", "has extension M?", "", false);
+    let _has_a = setting.add_bool("has_a", "has extension A?", "", false);
+    let _has_f = setting.add_bool("has_f", "has extension F?", "", false);
+    let _has_d = setting.add_bool("has_d", "has extension D?", "", false);
+    let _has_v = setting.add_bool("has_v", "has extension V?", "", false);
+    let _has_b = setting.add_bool("has_b", "has extension B?", "", false);
+    let _has_c = setting.add_bool("has_c", "has extension C?", "", false);
+    let _has_zbkb = setting.add_bool("has_zbkb", "has extension zbkb?", "", false);
+
+    let _has_zicsr = setting.add_bool("has_zicsr", "has extension zicsr?", "", false);
+    let _has_zifencei = setting.add_bool("has_zifencei", "has extension zifencei?", "", false);
+
+    setting.build()
+}
+
+pub(crate) fn define(shared_defs: &mut SharedDefinitions) -> TargetIsa {
+    let settings = define_settings(&shared_defs.settings);
+    TargetIsa::new("riscv64", settings)
+}

cranelift/codegen/src/binemit/mod.rs

@@ -66,6 +66,13 @@ pub enum Reloc {
     /// This is equivalent to `R_AARCH64_TLSGD_ADD_LO12_NC` in the [aaelf64](https://github.com/ARM-software/abi-aa/blob/2bcab1e3b22d55170c563c3c7940134089176746/aaelf64/aaelf64.rst#relocations-for-thread-local-storage)
     Aarch64TlsGdAddLo12Nc,
 
+    /// procedure call.
+    /// call symbol
+    /// expands to the following assembly and relocation:
+    /// auipc ra, 0
+    /// jalr ra, ra, 0
+    RiscvCall,
+
     /// s390x TLS GD64 - 64-bit offset of tls_index for GD symbol in GOT
     S390xTlsGd64,
     /// s390x TLS GDCall - marker to enable optimization of TLS calls
@@ -87,6 +94,7 @@ impl fmt::Display for Reloc {
             Self::X86GOTPCRel4 => write!(f, "GOTPCRel4"),
             Self::X86SecRel => write!(f, "SecRel"),
             Self::Arm32Call | Self::Arm64Call => write!(f, "Call"),
+            Self::RiscvCall => write!(f, "RiscvCall"),
 
             Self::ElfX86_64TlsGd => write!(f, "ElfX86_64TlsGd"),
             Self::MachOX86_64Tlv => write!(f, "MachOX86_64Tlv"),

cranelift/codegen/src/isa/mod.rs

@@ -66,6 +66,9 @@ pub mod x64;
 #[cfg(feature = "arm64")]
 pub(crate) mod aarch64;
 
+#[cfg(feature = "riscv64")]
+pub mod riscv64;
+
 #[cfg(feature = "s390x")]
 mod s390x;
 
@@ -97,6 +100,7 @@ pub fn lookup(triple: Triple) -> Result<Builder, LookupError> {
         }
         Architecture::Aarch64 { .. } => isa_builder!(aarch64, (feature = "arm64"), triple),
         Architecture::S390x { .. } => isa_builder!(s390x, (feature = "s390x"), triple),
+        Architecture::Riscv64 { .. } => isa_builder!(riscv64, (feature = "riscv64"), triple),
         _ => Err(LookupError::Unsupported),
     }
 }