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Codegen fix fcvt_from_sint.f32 with small types on riscv64. #5964

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merged 4 commits into from
Mar 10, 2023
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Codegen fix fcvt_from_sint.f32 with small types on riscv64. #5964

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5e13396
fix issue5952
yuyang-ok Mar 8, 2023
78d7074
We should only extend i8 and i16
yuyang-ok Mar 8, 2023
7c63215
remove extra space
yuyang-ok Mar 8, 2023
15e1e42
move some code
yuyang-ok Mar 10, 2023
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7 changes: 7 additions & 0 deletions cranelift/codegen/src/isa/riscv64/inst.isle
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Original file line number Diff line number Diff line change
Expand Up @@ -2122,6 +2122,13 @@
(ones Reg (load_imm12 -1)))
(value_reg (gen_select_reg (IntCC.Equal) zero input zero ones))))

(decl normalize_fcvt_from_int (ValueRegs Type ExtendOp) ValueRegs)
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(rule 2 (normalize_fcvt_from_int r (fits_in_16 ty) op)
(extend r op ty $I64))
(rule 1 (normalize_fcvt_from_int r _ _)
r)


;; Bitwise-or the two registers that make up the 128-bit value, then recurse as
;; though it was a 64-bit value.
(rule
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4 changes: 2 additions & 2 deletions cranelift/codegen/src/isa/riscv64/lower.isle
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Original file line number Diff line number Diff line change
Expand Up @@ -802,12 +802,12 @@
;;;;; Rules for `fcvt_from_sint`;;;;;;;;;
(rule
(lower (has_type to (fcvt_from_sint v @ (value_type from))))
(fpu_rr (int_convert_2_float_op from $true to) to v))
(fpu_rr (int_convert_2_float_op from $true to) to (normalize_fcvt_from_int v from (ExtendOp.Signed))))

;;;;; Rules for `fcvt_from_uint`;;;;;;;;;
(rule
(lower (has_type to (fcvt_from_uint v @ (value_type from))))
(fpu_rr (int_convert_2_float_op from $false to) to v))
(fpu_rr (int_convert_2_float_op from $false to) to (normalize_fcvt_from_int v from (ExtendOp.Zero))))

;;;;; Rules for `symbol_value`;;;;;;;;;
(rule
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28 changes: 20 additions & 8 deletions cranelift/filetests/filetests/isa/riscv64/fcvt-small.clif
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Original file line number Diff line number Diff line change
Expand Up @@ -10,12 +10,14 @@ block0(v0: i8):

; VCode:
; block0:
; fcvt.s.lu fa0,a0
; andi t2,a0,255
; fcvt.s.lu fa0,t2
; ret
;
; Disassembled:
; block0: ; offset 0x0
; fcvt.s.lu fa0, a0
; andi t2, a0, 0xff
; fcvt.s.lu fa0, t2
; ret

function u0:0(i8) -> f64 {
Expand All @@ -26,12 +28,14 @@ block0(v0: i8):

; VCode:
; block0:
; fcvt.d.lu fa0,a0
; andi t2,a0,255
; fcvt.d.lu fa0,t2
; ret
;
; Disassembled:
; block0: ; offset 0x0
; fcvt.d.lu fa0, a0
; andi t2, a0, 0xff
; fcvt.d.lu fa0, t2
; ret

function u0:0(i16) -> f32 {
Expand All @@ -42,12 +46,16 @@ block0(v0: i16):

; VCode:
; block0:
; fcvt.s.lu fa0,a0
; slli t2,a0,48
; srli a1,t2,48
; fcvt.s.lu fa0,a1
; ret
;
; Disassembled:
; block0: ; offset 0x0
; fcvt.s.lu fa0, a0
; slli t2, a0, 0x30
; srli a1, t2, 0x30
; fcvt.s.lu fa0, a1
; ret

function u0:0(i16) -> f64 {
Expand All @@ -58,12 +66,16 @@ block0(v0: i16):

; VCode:
; block0:
; fcvt.d.lu fa0,a0
; slli t2,a0,48
; srli a1,t2,48
; fcvt.d.lu fa0,a1
; ret
;
; Disassembled:
; block0: ; offset 0x0
; fcvt.d.lu fa0, a0
; slli t2, a0, 0x30
; srli a1, t2, 0x30
; fcvt.d.lu fa0, a1
; ret

function u0:0(f32) -> i8 {
Expand Down
14 changes: 14 additions & 0 deletions cranelift/filetests/filetests/runtests/issue5952.clif
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Original file line number Diff line number Diff line change
@@ -0,0 +1,14 @@
test interpret
test run
target aarch64
target x86_64
target s390x
target riscv64

function %a(i16 uext) -> f32 {
block0(v0: i16):
v1 = fcvt_from_sint.f32 v0
return v1
}

; run: %a(-12800) == -0x1.900000p13