Enhancing verilog composer

[ganeshgore]

Enhancing Verilog composer functionality, adding the following parameters
definition_list : Specify a list of definitions to compose, default it writes everything
write_blackbox : bool, to skip writing black-box

I added tests also let me know what you think.

[jacobdbrown4]

These look like good enhancements.

Also, it's failing the Travis CI test for python 3.5. In order to get it to pass, you need to specify each dict() as an OrderedDict(). The same goes for PR 159 and 162.

[ganeshgore]

Those are old tests I don't know why they are failing now, anyways using OrderDict makes sense I will update that

[ganeshgore]

This is fixed if you planned to merge. I will update other PRs with master

[jacobdbrown4]

Because SpyDrNet is available through PyPi, we periodically do new releases. When we do this, we update the master branch and then publish the updated package on PyPi. To help maintain this procedure, we'd like it if you could change the pull request to merge your branch into a new branch I created called "ganesh_contributions". Then we can begin merging your pull requests and then, when ready, we can merge it into master and release the updated code all at once. Are you able to do that?

[ganeshgore]

That sounds great. I can do that.