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commit 569c433
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Wed Nov 20 15:14:20 2024 -0800

    rsvd placeholders are sw=r,hw=w to help future DMI updates be more maintainable

commit afa06d5
Author: Nitsirks <michnorris@microsoft.com>
Date:   Wed Nov 20 13:06:40 2024 -0800

    adding rsvd fields to better maintain dmi read/writes

commit c48bda8
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Wed Nov 20 13:00:28 2024 -0800

    Shift FUSE REG offsets to better match 1.1 legacy offsets

commit 966f37c
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Wed Nov 20 12:44:31 2024 -0800

    Update Subsystem mode link from main spec; describe straps and generic functions; update debug_intent

commit 48ddd48
Author: Michael Norris <michnorris@microsoft.com>
Date:   Wed Nov 20 20:29:22 2024 +0000

    MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/tap_mbox_integ' with updated timestamp and hash after successful run

commit 44b2136
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Tue Nov 19 17:39:22 2024 -0800

    Rename SS_STRAP_RSVD to SS_STRAP_GENERIC. Add SS regs to external regs docs list.

commit 4924e5a
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Tue Nov 19 15:14:54 2024 -0800

    Fix strap bit size in integ spec

commit 05a14df
Author: Michael Norris <michnorris@microsoft.com>
Date:   Tue Nov 19 23:34:50 2024 +0000

    MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/tap_mbox_integ' with updated timestamp and hash after successful run

commit bc82cbe
Author: Nitsirks <michnorris@microsoft.com>
Date:   Tue Nov 19 14:33:13 2024 -0800

    fixing polarity of security state unlock out of reset

commit 6adcda0
Author: Michael Norris <michnorris@microsoft.com>
Date:   Tue Nov 19 21:46:30 2024 +0000

    MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/tap_mbox_integ' with updated timestamp and hash after successful run

commit 8756524
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Tue Nov 19 12:45:24 2024 -0800

    Fix a few comments that refer to AXI ID (now AXI USER)

commit 979693f
Merge: ae4b897 4ae54c3
Author: Nitsirks <michnorris@microsoft.com>
Date:   Tue Nov 19 12:42:44 2024 -0800

    Merge branch 'main' into user/dev/michnorris/tap_mbox_integ

commit ae4b897
Author: Caleb <11879229+calebofearth@users.noreply.github.com>
Date:   Tue Nov 19 12:25:54 2024 -0800

    [RTL] Convert AXI_ID to AXI_USER (#642)

    * Convert AXI_ID to AXI_USER

    * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-axi-user' with updated timestamp and hash after successful run

    * Revert default user value of 1 - this is driven in TB when needed

    * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-axi-user' with updated timestamp and hash after successful run

commit 48828bd
Author: Michael Norris <michnorris@microsoft.com>
Date:   Tue Nov 19 19:06:40 2024 +0000

    MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/tap_mbox_integ' with updated timestamp and hash after successful run

commit a7c651c
Author: Nitsirks <michnorris@microsoft.com>
Date:   Tue Nov 19 09:59:51 2024 -0800

    revert the live security state capture, instead capture on reset
    only update the security state capture if dbg level is appropriately set

commit 9f6b72e
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Tue Nov 19 09:48:08 2024 -0800

    Remove ss_dbg_prod_enable output bit

commit 4f51abf
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Mon Nov 18 19:35:00 2024 -0800

    in utils.sh: 'date +%s' is more portable than 'EPOCHSECONDS'

commit 5f389c9
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Mon Nov 18 18:58:39 2024 -0800

    Remove unused signal declarations

commit 6665d97
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Mon Nov 18 18:57:28 2024 -0800

    Remove unused signal declarations

commit ddfb3d8
Merge: b0a5fde 0d787f8
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Mon Nov 18 16:24:52 2024 -0800

    Merge remote-tracking branch 'chips/cwhitehead-msft-straps-regs-2p0' into user/dev/michnorris/tap_mbox_integ

commit 0d787f8
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Mon Nov 18 16:23:25 2024 -0800

    Addressing tweak in fuse_reg to better preserve legacy offsets

commit b0a5fde
Author: Nitsirks <michnorris@microsoft.com>
Date:   Mon Nov 18 15:53:51 2024 -0800

    typo

commit 231c5da
Author: Nitsirks <michnorris@microsoft.com>
Date:   Mon Nov 18 15:31:16 2024 -0800

    reverting change for github issue 422 - rejected

commit f21a069
Author: Nitsirks <michnorris@microsoft.com>
Date:   Mon Nov 18 15:30:16 2024 -0800

    adding readable hw/fw erro rencodings to uncore tap

commit 5fd1b23
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Mon Nov 18 15:29:10 2024 -0800

    Increase SS_GENERIC_FW_EXEC_CTRL width to 128b

commit 9021681
Author: Nitsirks <michnorris@microsoft.com>
Date:   Mon Nov 18 15:04:11 2024 -0800

    missing arcs for dlen latching for new tap mode state transitions

commit 42d9de4
Author: Nitsirks <michnorris@microsoft.com>
Date:   Mon Nov 18 15:03:40 2024 -0800

    github issue 422 - reset value of device lifecycle UNPROVISIONED

commit 1664a10
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Mon Nov 18 14:49:20 2024 -0800

    Rename SS_SOC_IFC_BASE_ADDR to CPTRA; make SS_GENERIC_FW_EXEC_CTRL 128b; Key Manifest Mask Fuse->256b

commit 2e4feda
Author: Nitsirks <michnorris@microsoft.com>
Date:   Mon Nov 18 14:40:57 2024 -0800

    fixing port list
    fixed signal name in soc ifc after moving from caliptra top

commit cb5faf3
Author: Nitsirks <michnorris@microsoft.com>
Date:   Mon Nov 18 14:14:51 2024 -0800

    removed capture condition on security state wires
    moved dmi reg mode masking to inside soc ifc top
    fixed register permissions for DBG REQ
    added flush and debug condition for lifecycle states NOT in MANUF or PROD

commit 6592f42
Author: Nitsirks <michnorris@microsoft.com>
Date:   Mon Nov 18 11:15:35 2024 -0800

    fixing latch

commit 3c5e734
Merge: 1ecf6ae 227b1d5
Author: Nitsirks <michnorris@microsoft.com>
Date:   Mon Nov 18 11:09:28 2024 -0800

    Merge branch 'main' into user/dev/michnorris/tap_mbox_integ

commit 1ecf6ae
Merge: 1614171 aa362ea
Author: Nitsirks <michnorris@microsoft.com>
Date:   Mon Nov 18 10:23:53 2024 -0800

    Merge branch 'main' into user/dev/michnorris/tap_mbox_integ

commit 1614171
Author: Nitsirks <michnorris@microsoft.com>
Date:   Sun Nov 17 12:59:32 2024 -0800

    adding tap interface to new registers

commit dcc5525
Merge: 8e5be01 f78dedb
Author: Nitsirks <michnorris@microsoft.com>
Date:   Sun Nov 17 09:05:03 2024 -0800

    Merge branch 'cwhitehead-msft-straps-regs-2p0' into user/dev/michnorris/tap_mbox_integ

commit f78dedb
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Sat Nov 16 22:17:01 2024 -0800

    Syntax fixes; cleanup for clean compile; regenerated RDL; fixed port connections

commit 6d80e1c
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Fri Nov 15 18:15:54 2024 -0800

    Latest register set + generated RDL outputs + integ spec updates. Does not compile.

commit 8e5be01
Author: Nitsirks <michnorris@microsoft.com>
Date:   Fri Nov 15 13:50:01 2024 -0800

    adding tap state to mailbox for tap mailbox feature.

commit dbf52da
Author: Caleb <11879229+calebofearth@users.noreply.github.com>
Date:   Fri Nov 15 11:35:44 2024 -0800

    [TB] Update soc_ifc C lib to support import by caliptra-ss (#637)

    * Remove inline fn in header so it can be included to caliptra-ss

    * Restamp repo after rebase

commit a8aca5f
Author: Michael Norris <108370498+Nitsirks@users.noreply.github.com>
Date:   Thu Nov 14 15:16:39 2024 -0800

    csr hmac signing key (#630)

    * csr hmac signing key implementation
    uvm hmac collaterals updated to validate the new flow

    * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/csr_hmac_key' with updated timestamp and hash after successful run

    * adding swwe to all control bits so they can only be set when ready

    * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/csr_hmac_key' with updated timestamp and hash after successful run

    * updating specifications for csr hmac key and key vault changes

    * details about csr mode in hw spec

    * MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/michnorris/csr_hmac_key' with updated timestamp and hash after successful run

commit 49d6857
Author: Caleb <11879229+calebofearth@users.noreply.github.com>
Date:   Wed Nov 13 16:25:28 2024 -0800

    [RTL] Disable RV USER_MODE and SMEPMP (#633)

    * Reorganize defines.h to match ordering from VeeR repo latest -- but don't change any macro values or add new ones

    * Disable USER_MODE and SMEPMP (PMP is enabled by default, per chipsalliance/Cores-VeeR-EL2#258)

    * Syntax fix for clean lint (multibit signal used as boolean)

    * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-rv-dis-smepmp' with updated timestamp and hash after successful run

commit c327135
Author: Nitsirks <michnorris@microsoft.com>
Date:   Fri Nov 15 14:27:02 2024 -0800

    start of tap mailbox changes

commit bd5cb84
Author: Caleb <11879229+calebofearth@users.noreply.github.com>
Date:   Tue Nov 12 12:37:22 2024 -0800

    [ENV] Fix path to smoke_test_doe_cg in nightly directed regression list (#632)

    * Fix path to smoke_test_doe_cg in nightly dir. regression list

    * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-dir-regr-fix' with updated timestamp and hash after successful run

commit 1b7a6a1
Author: Caleb <11879229+calebofearth@users.noreply.github.com>
Date:   Mon Nov 11 18:02:52 2024 -0800

    Upgrade RV core to latest, enable SMEPMP and User Mode (#628)

    * Override reset_vec to 0x0 with script call option (no longer need to hand-edit script)

    * Refactor iccm config for maintainability

    * VeeR core update to latest design file version

    * Add rev info file to indicate VeeR version consumed

    * Remove JTAG IDCODE command, as previously done

    * Route a core_enable signal to conditionally disable internal core TAP access

    * Add a dmi_active output signal

    * Updated RV instance for compatibility with latest DMI export signals

    * Updated VeeR mem export interface splits data/ecc

    * Enable SMEPMP with 64-entries; enable user-mode

    * Update directory includes/dependencies

    * Requires soc_ifc_pkg

    * Port width fix

    * First index is for bank number - fix

    * Move localparams to top of file, so they exist at the first usage

    * Update license headers on RV core

    * Regenerate file lists

    * Revert latch fix that causes Verilator failures

    * Replace 'repeat' (verilator dislikes) with for-loop; add missing begin-end

    * MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-rv-upgrade' with updated timestamp and hash after successful run

commit a0d92c7
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Wed Nov 13 16:31:07 2024 -0800

    Add MCI base address strap

commit 4707887
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Wed Nov 13 16:21:52 2024 -0800

    More robust arg parsing

commit 4b6f86a
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Wed Nov 13 15:57:36 2024 -0800

    Remove fuse_life_cycle from soc_ifc_tb

commit ad9c366
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Wed Nov 13 15:52:45 2024 -0800

    Add fw/hw cap, debug_auth_pk regs, debug unlock tokens, subsystem strap bank; rm lifecycle fuse; rename ready_for_fw; regenerate RDL

commit c1f9dce
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Wed Nov 13 15:45:52 2024 -0800

    Use cmd line arg to build covergroups/sample include files

commit 89a3630
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Tue Nov 12 11:09:59 2024 -0800

    Move fuse_owner_pk_hash to CPTRA_OWNER_PK_HASH

    * Add new dedicated lock register for CPTRA_OWNER_PK_HASH
    * Drive CPTRA_OWNER_PK_HASH swwel appropriately
    * Update val collateral
    * Update coverage groups
    * Regenerate RDL outputs from changes
    * Addresses #540

commit 972038f
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Mon Nov 11 17:42:02 2024 -0800

    Regenerate with fuse regs changes

commit ef12ba3
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Mon Nov 11 17:36:00 2024 -0800

    Remove fuse_lms_verify; add fuse_mldsa_revocation, per chipsalliance/Caliptra#235

commit c29d13c
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Fri Nov 8 14:46:40 2024 -0800

    New subsystem reg region in soc_ifc_reg

commit b356e74
Author: Caleb Whitehead <cwhitehead@microsoft.com>
Date:   Fri Nov 8 14:46:22 2024 -0800

    Add active mode bit to HW_CONFIG reg
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4 changes: 2 additions & 2 deletions .github/scripts/utils.sh
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Expand Up @@ -32,8 +32,8 @@ wait_for_phrase () {
fi

# Wait for the phrase
DEADLINE=$((${EPOCHSECONDS} + 30))
while [ ${EPOCHSECONDS} -lt ${DEADLINE} ]
DEADLINE=$(($(date +%s) + 30))
while [ $(date +%s) -lt ${DEADLINE} ]
do
# Check for the phrase
grep "$2" "$1" >/dev/null
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2 changes: 1 addition & 1 deletion .github/workflow_metadata/pr_hash
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6104519ceefcd79a47c8c890b053f79f50e15d8213ab0685984df75f95b1273d5eff69ea0dc07cd2d53536d9ed52f88a
d1f7aaef6d9d5747a0c833193c02f1ed0c01a5ae581d028e1c415520a50ea8573ad30c65b490d78f2ee4f797ecd9345e
2 changes: 1 addition & 1 deletion .github/workflow_metadata/pr_timestamp
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37 changes: 25 additions & 12 deletions docs/CaliptraIntegrationSpecification.md
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Expand Up @@ -63,8 +63,7 @@ The following table describes integration parameters.
| **Defines** | **Defines file** | **Description** |
| :--------- | :--------- | :--------- |
| CALIPTRA_INTERNAL_TRNG | config_defines.svh | Defining this enables the internal TRNG source. |
| CALIPTRA_INTERNAL_UART | config_defines.svh | Defining this enables the internal UART. |
| CALIPTRA_INTERNAL_QSPI | config_defines.svh | Defining this enables the internal QSPI. |
| CALIPTRA_MODE_SUBSYSTEM | config_defines.svh | Defining this enables Caliptra to operate in subsystem mode. This includes features such as the debug unlock flow, AXI DMA (for recovery flow), subsystem level straps, among other capabilites. See [Caliptra Subsystem Architectural Flows](https://github.com/chipsalliance/Caliptra/blob/main/doc/Caliptra.md#caliptra-subsystem-architectural-flows) for more details |
| USER_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in [clk_gate.sv](../src/libs/rtl/clk_gate.sv). USER_ICG replaces the clock gating module, CALIPTRA_ICG, defined in [caliptra_icg.sv](../src/libs/rtl/caliptra_icg.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_ICG. |
| TECH_SPECIFIC_ICG | config_defines.svh | Defining this causes the custom, integrator-defined clock gate module (indicated by the USER_ICG macro) to be used in place of the native Caliptra clock gate module. |
| USER_EC_RV_ICG | config_defines.svh | If added by an integrator, provides the name of the custom clock gating module that is used in the RISC-V core. USER_EC_RV_ICG replaces the clock gating module, TEC_RV_ICG, defined in [beh_lib.sv](../src/riscv_core/veer_el2/rtl/lib/beh_lib.sv). This substitution is only performed if integrators also define TECH_SPECIFIC_EC_RV_ICG. |
Expand Down Expand Up @@ -150,12 +149,25 @@ The following tables describe the interface signals.
| jtag_trst_n | 1 | input | Asynchronous assertion<br>Synchronous deassertion to jtag_tck | |
| jtag_tdo | 1 | output | Synchronous to jtag_tck | |

*Table 10: UART interface*

| Signal name | Width | Driver | Synchronous (as viewed from Caliptra’s boundary) | Description |
| :--------- | :--------- | :--------- | :--------- | :--------- |
| uart_tx | 1 | output | | UART transmit pin |
| uart_rx | 1 | input | | UART receive pin |
*Table 10: Subsystem Straps and Control*

| Signal name | Width | Driver | Synchronous (as viewed from Caliptra’s boundary) | Description |
| :---------- | :--------- | :--------- | :----------------------------------------------- | :--------- |
| strap_ss_caliptra_base_addr | 64 | Input Strap | Synchronous to clk | |
| strap_ss_mci_base_addr | 64 | Input Strap | Synchronous to clk | |
| strap_ss_recovery_ifc_base_addr | 64 | Input Strap | Synchronous to clk | |
| strap_ss_otp_fc_base_addr | 64 | Input Strap | Synchronous to clk | |
| strap_ss_uds_seed_base_addr | 64 | Input Strap | Synchronous to clk | |
| strap_ss_prod_debug_unlock_auth_pk_hash_reg_bank_offset | 32 | Input Strap | Synchronous to clk | |
| strap_ss_num_of_prod_debug_unlock_auth_pk_hashes | 32 | Input Strap | Synchronous to clk | |
| strap_ss_strap_generic_0 | 32 | Input Strap | Synchronous to clk | |
| strap_ss_strap_generic_1 | 32 | Input Strap | Synchronous to clk | |
| strap_ss_strap_generic_2 | 32 | Input Strap | Synchronous to clk | |
| strap_ss_strap_generic_3 | 32 | Input Strap | Synchronous to clk | |
| ss_debug_intent | 1 | Input Strap | Synchronous to clk | Sample on cold reset. Used in Subsystem mode only. Indicates that the SoC is in debug mode and a user intends to request unlock of debug mode through the TAP mailbox. In Passive mode, integrators shall tie this input to 0. |
| ss_dbg_manuf_enable | 1 | Output | Synchronous to clk | |
| ss_soc_dbg_unlock_level | 64 | Output | Synchronous to clk | |
| ss_generic_fw_exec_ctrl | 128 | Output | Synchronous to clk | |

*Table 11: Security and miscellaneous*

Expand Down Expand Up @@ -228,6 +240,7 @@ Caliptra firmware internally has the capability to force release the mailbox bas
### Straps

Straps are signal inputs to Caliptra that are sampled once on reset exit, and the latched value persists throughout the remaining uptime of the system. Straps are sampled on either caliptra pwrgood signal deassertion or cptra\_noncore\_rst\_b deassertion – refer to interface table for list of straps.
In 2.0, Caliptra adds support for numerous Subsystem-level straps. These straps are initialized on cold boot to the value from the external port, but may also be rewritten by the SoC firmware at any time prior to CPTRA_FUSE_WR_DONE being set. Once written and locked, the values of these straps persist until a cold reset.

### Obfuscation key

Expand All @@ -247,11 +260,11 @@ SoC must ensure that there are no SCAN cells on the flops that latch this key in

## Late binding interface signals

The interface signals GENERIC\_INPUT\_WIRES and GENERIC\_OUTPUT\_WIRES are placeholders on the SoC interface reserved for late binding features. This may include any feature that is required for correct operation of the design in the final integrated SoC and that may not be accommodated through existing interface signaling (such as the mailbox).
The interface signals GENERIC\_INPUT\_WIRES, GENERIC\_OUTPUT\_WIRES, and strap\_ss\_strap\_generic\_N are placeholders on the SoC interface reserved for late binding features. This may include any feature that is required for correct operation of the design in the final integrated SoC and that may not be accommodated through existing interface signaling (such as the mailbox).

While these late binding interface pins are generic in nature until assigned a function, integrators must not define non-standard use cases for these pins. Defining standard use cases ensures that the security posture of Caliptra in the final implementation is not degraded relative to the consortium design intent. Bits in GENERIC\_INPUT\_WIRES that don't have a function defined in Caliptra must be tied to a 0-value. These undefined input bits shall not be connected to any flip flops (which would allow run-time transitions on the value).
While these late binding interface pins are generic in nature until assigned a function, integrators must not define non-standard use cases for these pins. Defining standard use cases ensures that the security posture of Caliptra in the final implementation is not degraded relative to the consortium design intent. Bits in GENERIC\_INPUT\_WIRES and strap\_ss\_strap\_generic\_N that don't have a function defined in Caliptra must be tied to a 0-value. These undefined input bits shall not be connected to any flip flops (which would allow run-time transitions on the value).

Each wire connects to a register in the SoC Interface register bank through which communication to the internal microprocessor may be facilitated. Each signal is 64 bits in size.
Each wire connects to a register in the SoC Interface register bank through which communication to the internal microprocessor may be facilitated. Each of the generic wire signals is 64 bits in size. The size of the generic strap is indicated in Table 10.

Activity on any bit of the GENERIC\_INPUT\_WIRES triggers a notification interrupt to the microcontroller indicating a bit toggle.

Expand Down Expand Up @@ -514,7 +527,7 @@ The following memories are exported:
* Instruction Closely-Coupled Memory (ICCM)
* Data Closely Coupled Memory (DCCM)

Table 4 indicates the signals contained in the memory interface. Direction is relative to the exported memory wrapper that is instantiated outside of the Caliptra subsystem (that is, from the testbench perspective).
Table 8 indicates the signals contained in the memory interface. Direction is relative to the exported memory wrapper that is instantiated outside of the Caliptra subsystem (that is, from the testbench perspective).

## SRAM timing behavior
* [Writes] Input wren signal is asserted simultaneously with input data and address. Input data is stored at the input address 1 clock cycle later.
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