Merge pull request #1481 from freechipsproject/driver-deprecations

Remove Deprecated Usages of chisel3.Driver, CircuitForm

src/main/scala/chisel3/Driver.scala

@@ -61,6 +61,7 @@ trait BackendCompilationUtilities extends FirrtlBackendCompilationUtilities {
 /**
   * This family provides return values from the chisel3 and possibly firrtl compile steps
   */
+@deprecated("This will be removed in Chisel 3.5", "Chisel3 3.4")
 trait ChiselExecutionResult
 
 /**
@@ -69,6 +70,7 @@ trait ChiselExecutionResult
   * @param emitted            The emitted Chirrrl text
   * @param firrtlResultOption Optional Firrtl result, @see freechipsproject/firrtl for details
   */
+@deprecated("This will be removed in Chisel 3.5", "Chisel 3.4")
 case class ChiselExecutionSuccess(
                                   circuitOption: Option[Circuit],
                                   emitted: String,
@@ -80,6 +82,7 @@ case class ChiselExecutionSuccess(
   *
   * @param message A clue might be provided here.
   */
+@deprecated("This will be removed in Chisel 3.5", "Chisel 3.4")
 case class ChiselExecutionFailure(message: String) extends ChiselExecutionResult
 
 @deprecated("Please switch to chisel3.stage.ChiselStage. Driver will be removed in 3.4.", "3.2.4")

src/main/scala/chisel3/compatibility.scala

@@ -6,6 +6,7 @@
 import chisel3._    // required for implicit conversions.
 import chisel3.experimental.chiselName
 import chisel3.util.random.FibonacciLFSR
+import chisel3.stage.{ChiselCircuitAnnotation, ChiselOutputFileAnnotation, ChiselStage, phases}
 
 package object Chisel {     // scalastyle:ignore package.object.name number.of.types number.of.methods
   import chisel3.internal.firrtl.Width
@@ -395,21 +396,32 @@ package object Chisel {     // scalastyle:ignore package.object.name number.of.t
   implicit class fromIntToWidth(x: Int) extends chisel3.fromIntToWidth(x)
 
   type BackendCompilationUtilities = firrtl.util.BackendCompilationUtilities
-  val Driver = chisel3.Driver
   val ImplicitConversions = chisel3.util.ImplicitConversions
 
   // Deprecated as of Chisel3
   object chiselMain {
     import java.io.File
 
+    private var target_dir: Option[String] = None
+
+    private def parseArgs(args: Array[String]): Unit = {
+      for (i <- args.indices) {
+        if (args(i) == "--targetDir") {
+          target_dir = Some(args(i + 1))
+        }
+      }
+    }
+
     def apply[T <: Module](args: Array[String], gen: () => T): Unit =
       Predef.assert(false, "No more chiselMain in Chisel3")
 
     def run[T <: Module] (args: Array[String], gen: () => T): Unit = {
-      val circuit = Driver.elaborate(gen)
-      Driver.parseArgs(args)
-      val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
-      Driver.dumpFirrtl(circuit, Option(output_file))
+      val circuit = ChiselStage.elaborate(gen())
+      parseArgs(args)
+      val output_file = new File(target_dir.getOrElse(new File(".").getCanonicalPath) + "/" + circuit.name + ".fir")
+
+      (new phases.Emitter).transform(Seq(ChiselCircuitAnnotation(circuit),
+                                         ChiselOutputFileAnnotation(output_file.toString)))
     }
   }
 

src/main/scala/chisel3/internal/firrtl/Emitter.scala

@@ -186,7 +186,7 @@ private class Emitter(circuit: Circuit) {
   private def withIndent(f: => Unit) { indent(); f; unindent() }
 
   private val res = new StringBuilder()
-  res ++= s";${Driver.chiselVersionString}\n"
+  res ++= s";${BuildInfo.toString}\n"
   res ++= s"circuit ${circuit.name} : "
   withIndent { circuit.components.foreach(c => res ++= emit(c)) }
   res ++= newline

src/main/scala/chisel3/testers/TesterDriver.scala

@@ -7,34 +7,53 @@ import java.io._
 
 import chisel3.aop.Aspect
 import chisel3.experimental.RunFirrtlTransform
-import chisel3.stage.phases.AspectPhase
-import chisel3.stage.{ChiselCircuitAnnotation, ChiselStage, DesignAnnotation}
+import chisel3.stage.phases.{AspectPhase, Convert, Elaborate, Emitter}
+import chisel3.stage.{
+  ChiselCircuitAnnotation,
+  ChiselGeneratorAnnotation,
+  ChiselOutputFileAnnotation,
+  ChiselStage,
+  DesignAnnotation
+}
 import firrtl.{Driver => _, _}
+import firrtl.options.{Dependency, Phase, PhaseManager}
+import firrtl.stage.{FirrtlCircuitAnnotation, FirrtlStage}
 import firrtl.transforms.BlackBoxSourceHelper.writeResourceToDirectory
 
 object TesterDriver extends BackendCompilationUtilities {
 
+  /** Set the target directory to the name of the top module after elaboration */
+  final class AddImplicitTesterDirectory extends Phase {
+    override def prerequisites = Seq(Dependency[Elaborate])
+    override def optionalPrerequisites = Seq.empty
+    override def optionalPrerequisiteOf = Seq(Dependency[Emitter])
+    override def invalidates(a: Phase) = false
+
+    override def transform(a: AnnotationSeq) = a.flatMap {
+      case a@ ChiselCircuitAnnotation(circuit) =>
+        Seq(a, TargetDirAnnotation(
+              firrtl.util.BackendCompilationUtilities.createTestDirectory(circuit.name)
+                .getAbsolutePath
+                .toString))
+      case a => Seq(a)
+    }
+  }
+
   /** For use with modules that should successfully be elaborated by the
     * frontend, and which can be turned into executables with assertions. */
   def execute(t: () => BasicTester,
               additionalVResources: Seq[String] = Seq(),
               annotations: AnnotationSeq = Seq()
              ): Boolean = {
-    // Invoke the chisel compiler to get the circuit's IR
-    val (circuit, dut) = new chisel3.stage.ChiselGeneratorAnnotation(finishWrapper(t)).elaborate.toSeq match {
-      case Seq(ChiselCircuitAnnotation(cir), d:DesignAnnotation[_]) => (cir, d)
-    }
-
-    // Set up a bunch of file handlers based on a random temp filename,
-    // plus the quirks of Verilator's naming conventions
-    val target = circuit.name
+    val pm = new PhaseManager(
+      targets = Seq(Dependency[AddImplicitTesterDirectory],
+                    Dependency[Emitter],
+                    Dependency[Convert]))
 
-    val path = createTestDirectory(target)
-    val fname = new File(path, target)
+    val annotationsx = pm.transform(ChiselGeneratorAnnotation(t) +: annotations)
 
-    // For now, dump the IR out to a file
-    Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir")))
-    val firrtlCircuit = Driver.toFirrtl(circuit)
+    val target: String = annotationsx.collectFirst { case FirrtlCircuitAnnotation(cir) => cir.main }.get
+    val path = annotationsx.collectFirst { case TargetDirAnnotation(dir) => dir }.map(new File(_)).get
 
     // Copy CPP harness and other Verilog sources from resources into files
     val cppHarness =  new File(path, "top.cpp")
@@ -47,24 +66,7 @@ object TesterDriver extends BackendCompilationUtilities {
       writeResourceToDirectory(name, path)
     })
 
-    // Compile firrtl
-    val transforms = circuit.annotations.collect {
-      case anno: RunFirrtlTransform => anno.transformClass
-    }.distinct
-     .filterNot(_ == classOf[Transform])
-     .map { transformClass: Class[_ <: Transform] => transformClass.newInstance() }
-    val newAnnotations = circuit.annotations.map(_.toFirrtl).toList ++ annotations ++ Seq(dut)
-    val resolvedAnnotations = new AspectPhase().transform(newAnnotations).toList
-    val optionsManager = new ExecutionOptionsManager("chisel3") with HasChiselExecutionOptions with HasFirrtlOptions {
-      commonOptions = CommonOptions(topName = target, targetDirName = path.getAbsolutePath)
-      firrtlOptions = FirrtlExecutionOptions(compilerName = "verilog", annotations = resolvedAnnotations,
-                                             customTransforms = transforms,
-                                             firrtlCircuit = Some(firrtlCircuit))
-    }
-    firrtl.Driver.execute(optionsManager) match {
-      case _: FirrtlExecutionFailure => return false
-      case _ =>
-    }
+    (new FirrtlStage).execute(Array("--compiler", "verilog"), annotationsx)
 
     // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
     if ((verilogToCpp(target, path, additionalVFiles, cppHarness) #&&

src/test/scala/chiselTests/AnalogSpec.scala

@@ -3,6 +3,7 @@
 package chiselTests
 
 import chisel3._
+import chisel3.stage.ChiselStage
 import chisel3.util._
 import chisel3.testers.BasicTester
 import chisel3.experimental.{Analog, attach, BaseModule}
@@ -82,28 +83,28 @@ abstract class AnalogTester extends BasicTester {
     assert(reader.out === BusValue)
 }
 
-class AnalogSpec extends ChiselFlatSpec {
+class AnalogSpec extends ChiselFlatSpec with Utils {
   behavior of "Analog"
 
   it should "NOT be bindable to registers" in {
-    a [ChiselException] should be thrownBy {
-      elaborate { new Module {
+    a [ChiselException] should be thrownBy extractCause[ChiselException] {
+      ChiselStage.elaborate { new Module {
         val io = IO(new Bundle {})
         val reg = Reg(Analog(32.W))
       }}
     }
   }
 
   it should "NOT be bindable to a direction" in {
-    a [ChiselException] should be thrownBy {
-      elaborate { new Module {
+    a [ChiselException] should be thrownBy extractCause[ChiselException] {
+      ChiselStage.elaborate { new Module {
         val io = IO(new Bundle {
           val a = Input(Analog(32.W))
         })
       }}
     }
-    a [ChiselException] should be thrownBy {
-      elaborate { new Module {
+    a [ChiselException] should be thrownBy extractCause[ChiselException] {
+      ChiselStage.elaborate { new Module {
         val io = IO(new Bundle {
           val a = Output(Analog(32.W))
         })
@@ -112,7 +113,7 @@ class AnalogSpec extends ChiselFlatSpec {
   }
 
   it should "be flippable" in {
-    elaborate { new Module {
+    ChiselStage.elaborate { new Module {
       val io = IO(new Bundle {
         val a = Flipped(Analog(32.W))
       })
@@ -122,17 +123,17 @@ class AnalogSpec extends ChiselFlatSpec {
   // There is no binding on the type of a memory
   // Should this be an error?
   ignore should "NOT be a legal type for Mem" in {
-    a [ChiselException] should be thrownBy {
-      elaborate { new Module {
+    a [ChiselException] should be thrownBy extractCause[ChiselException] {
+      ChiselStage.elaborate { new Module {
         val io = IO(new Bundle {})
         val mem = Mem(16, Analog(32.W))
       }}
     }
   }
 
   it should "NOT be bindable to Mem ports" in {
-    a [ChiselException] should be thrownBy {
-      elaborate { new Module {
+    a [ChiselException] should be thrownBy extractCause[ChiselException] {
+      ChiselStage.elaborate { new Module {
         val io = IO(new Bundle {})
         val mem = Mem(16, Analog(32.W))
         val port = mem(5.U)
@@ -161,16 +162,16 @@ class AnalogSpec extends ChiselFlatSpec {
   }
 
   it should "error if any bulk connected more than once" in {
-    a [ChiselException] should be thrownBy {
-      elaborate(new Module {
+    a [ChiselException] should be thrownBy extractCause[ChiselException] {
+      ChiselStage.elaborate(new Module {
         val io = IO(new Bundle {})
         val wires = List.fill(3)(Wire(Analog(32.W)))
         wires(0) <> wires(1)
         wires(0) <> wires(2)
       })
     }
-    a [ChiselException] should be thrownBy {
-      elaborate(new Module {
+    a [ChiselException] should be thrownBy extractCause[ChiselException] {
+      ChiselStage.elaborate(new Module {
         val io = IO(new Bundle {})
         val wires = List.fill(2)(Wire(Analog(32.W)))
         wires(0) <> DontCare
@@ -180,13 +181,13 @@ class AnalogSpec extends ChiselFlatSpec {
   }
 
   it should "allow DontCare connection" in {
-    elaborate(new Module {
+    ChiselStage.elaborate(new Module {
       val io = IO(new Bundle {
         val a = Analog(1.W)
       })
       io.a := DontCare
     })
-    elaborate(new Module {
+    ChiselStage.elaborate(new Module {
       val io = IO(new Bundle {
         val a = Analog(1.W)
       })
@@ -199,14 +200,14 @@ class AnalogSpec extends ChiselFlatSpec {
       val x = Input(UInt(8.W))
       val y = Analog(8.W)
     }
-    elaborate(new Module {
+    ChiselStage.elaborate(new Module {
       val io = IO(new Bundle {
         val a = new MyBundle
       })
       val w = Wire(new MyBundle)
       w <> io.a
     })
-    elaborate(new Module {
+    ChiselStage.elaborate(new Module {
       val io = IO(new Bundle {
         val a = Vec(1, new MyBundle)
       })
@@ -295,4 +296,3 @@ class AnalogSpec extends ChiselFlatSpec {
     }, Seq("/chisel3/AnalogBlackBox.v"))
   }
 }
-