Fix argument list for verilogToCpp(). (#101)

chipsalliance · Feb 1, 2017 · db04bd6 · db04bd6
1 parent 6a814a7
commit db04bd6
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Showing 2 changed files with 2 additions and 3 deletions.
diff --git a/ChiselMain.scala b/ChiselMain.scala
@@ -72,7 +72,7 @@ object chiselMain {
         // Copy API files
         copyVerilatorHeaderFiles(context.targetDir.toString)
         // Generate Verilator
-        assert(chisel3.Driver.verilogToCpp(dutName, dutName, dir, Seq(), new File(s"$dutName-harness.cpp")).! == 0)
+        assert(chisel3.Driver.verilogToCpp(dutName, dir, Seq(), new File(s"$dutName-harness.cpp")).! == 0)
         // Compile Verilator
         assert(chisel3.Driver.cppToExe(dutName, dir).! == 0)
       case "vcs" | "glsim" =>

diff --git a/VerilatorBackend.scala b/VerilatorBackend.scala
@@ -326,11 +326,10 @@ private[iotesters] object setupVerilatorBackend {
 
         assert(
           chisel3.Driver.verilogToCpp(
-            circuit.name,
             circuit.name,
             dir,
             vSources = Seq(),
-            new File(cppHarnessFileName)
+            cppHarnessFile
           ).! == 0
         )
         assert(chisel3.Driver.cppToExe(circuit.name, dir).! == 0)