Switch statements should not point to "Conditional.scala" in generated verilog

[danielkasza]

Type of issue: feature request

Impact: no functional change

Development Phase: request

Other information

Example: https://scastie.scala-lang.org/vXpOaKjuQmmj91AUXLYGHQ

module Foo(
  input        clock,
  input        reset,
  input  [1:0] io_in,
  output [1:0] io_out
);
  wire  _T = 2'h0 == io_in; // @[Conditional.scala 37:30]
  wire  _T_1 = 2'h1 == io_in; // @[Conditional.scala 37:30]
  wire  _T_2 = 2'h2 == io_in; // @[Conditional.scala 37:30]
  wire  _T_3 = 2'h3 == io_in; // @[Conditional.scala 37:30]
  wire [1:0] _GEN_0 = _T_3 ? 2'h3 : 2'h0; // @[Conditional.scala 39:67]
  wire [1:0] _GEN_1 = _T_2 ? 2'h1 : _GEN_0; // @[Conditional.scala 39:67]
  wire [1:0] _GEN_2 = _T_1 ? 2'h0 : _GEN_1; // @[Conditional.scala 39:67]
  assign io_out = _T ? 2'h3 : _GEN_2; // @[main.scala 13:10 main.scala 16:14 main.scala 20:14 main.scala 24:14 main.scala 28:14]
endmodule

What is the current behavior?

Verilog lines generated from switch statement refer back to Conditional.scala.

What is the expected behavior?

These lines should instead refer back to the source line of the is statement..

What is the use case for changing the behavior?

It would make it easier to cross-reference the generated Verilog and the Scala source.
I ran into this because one of my modules fails formal verification due to unreachable cases in a switch.

[jackkoenig]

Thank you for the bug report! I believe this was fixed by #1618 (to be released in 3.4.1), but will verify before closing this issue.

[danielkasza]

I just tried this on e6192ea and I am still getting similar output.

[jackkoenig]

Ah yes, I misread the issue originally. This is a limitation that needs to be addressed, thank you for checking!