Fix broken links in docs

docs/src/wiki-deprecated/chisel3-vs-chisel2.md

@@ -89,7 +89,7 @@ for instructions on preparing your Chisel2 designs for Chisel3.
 ## Unsupported constructs
 *  `Mem(..., orderedWrites)` is no longer supported,
 *  masked writes are only supported for `Mem[Vec[_]]`,
-* Chisel3 Vecs must all have the same type, unlike with Chisel2. Use `MixedVec` (see [Bundles and Vecs](bundles-and-vecs)) for Vecs where the elements are of different types.
+* Chisel3 Vecs must all have the same type, unlike with Chisel2. Use `MixedVec` (see [Bundles and Vecs](../explanations/bundles-and-vecs)) for Vecs where the elements are of different types.
 *  connections between `UInt` and `SInt` are illegal.
 *  the `Node` class and object no longer exist (the class should have been private in Chisel2)
 *  `printf()` is defined in the Chisel object and produces simulation printf()'s.

docs/src/wiki-deprecated/reset.md

@@ -117,7 +117,7 @@ You can also cast to force the concrete type of reset.
 * `.asAsyncReset` will reinterpret a `Reset` as `AsyncReset`.
 
 You can then use `withReset` to use a cast reset as the implicit reset.
-See ["Multiple Clock Domains"](multi-clock) for more information about `withReset`.
+See ["Multiple Clock Domains"](../explanations/multi-clock) for more information about `withReset`.
 
 
 The following will make `myReg` as well as both `resetAgnosticReg`s synchronously reset: