Update reported width from div/rem to match FIRRTL results (bp #1748)

[mergify]

This is an automatic backport of pull request #1748 done by Mergify.

Cherry-pick of 98ce919 has failed:

On branch mergify/bp/3.2.x/pr-1748
Your branch is up to date with 'origin/3.2.x'.

You are currently cherry-picking commit 98ce9194.
  (fix conflicts and run "git cherry-pick --continue")
  (use "git cherry-pick --skip" to skip this patch)
  (use "git cherry-pick --abort" to cancel the cherry-pick operation)

Changes to be committed:
	modified:   chiselFrontend/src/main/scala/chisel3/Bits.scala
	modified:   src/test/scala/chiselTests/SIntOps.scala
	modified:   src/test/scala/chiselTests/UIntOps.scala
	modified:   src/test/scala/chiselTests/WidthSpec.scala

Unmerged paths:
  (use "git add/rm <file>..." as appropriate to mark resolution)
	deleted by us:   core/src/main/scala/chisel3/internal/firrtl/IR.scala

To fixup this pull request, you can check out it locally. See documentation: https://help.github.com/articles/checking-out-pull-requests-locally/

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[jackkoenig]

Closing all backports to versions older than 3.4.x