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Update reported width from div/rem to match FIRRTL results (bp #1748) #1768

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Update reported width from div/rem to match FIRRTL results (bp #1748) #1768

wants to merge 1 commit into from

Commits on Feb 1, 2021

  1. Update reported width from div/rem to match FIRRTL results (#1748) 

    * Update reported width from div/rem to match FIRRTL results

* Add tests for width of % and / on UInt and SInt

* Add loop-based test for known UInt/SInt op result widths

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 98ce919)

# Conflicts:
#	core/src/main/scala/chisel3/internal/firrtl/IR.scala
    @albert-magyar
    albert-magyar authored and mergify-bot committed Feb 1, 2021
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