[Scala3] Scala2 src compatibility changes for Scala3

[adkian-sifive]

Updates to cross-compiling sources in src/main:

• Add explicit imports as required by Dotty
• Replace do..while loops
• Move sources to src/main/scala-2 to stage for Scala3 implementation after v0.1

Contributor Checklist

• Did you add Scaladoc to every public function/method?
• Did you add at least one test demonstrating the PR?
• Did you delete any extraneous printlns/debugging code?
• Did you specify the type of improvement?
• Did you add appropriate documentation in docs/src?
• Did you request a desired merge strategy?
• Did you add text to be included in the Release Notes for this change?

Type of Improvement

• Feature (or new API)
• Internal or build-related (includes code refactoring/cleanup)

Desired Merge Strategy

• Rebase: You will rebase the PR onto master and it will be merged with a merge commit.

Release Notes

Sources were refactored and updated in preparation of upcoming Scala3 support

Reviewer Checklist (only modified by reviewer)

• Did you add the appropriate labels? (Select the most appropriate one based on the "Type of Improvement")
• Did you mark the proper milestone (Bug fix: 3.6.x, 5.x, or 6.x depending on impact, API modification or big change: 7.0)?
• Did you review?
• Did you check whether all relevant Contributor checkboxes have been checked?
• Did you do one of the following when ready to merge:
  • Squash: You/ the contributor Enable auto-merge (squash), clean up the commit message, and label with Please Merge.
  • Merge: Ensure that contributor has cleaned up their commit history, then merge with Create a merge commit.

[jackkoenig]

I'm not particularly fond of moving files to src/main/scala-2 which just delays needing to do the scala-2 scala-3 split, but I guess it's fine.

That being said, when splitting the shared code back in to src/main/scala, we must first git mv back to src/main/scala then split from there so that the git blame works properly in the Github UI.

[sequencer]

This caused RTL change in Rocket ALU, related code:
https://github.com/chipsalliance/t1/blob/336d0adddaf4c15eb23425193f9a560fc9ac8f26/rocketv/src/ALU.scala#L94

original:

module ALU(
  input         dw,
  input  [3:0]  fn,
  input  [31:0] in2,
                in1,
  output [31:0] out,
                adder_out,
  output        cmp_out
);

  wire [31:0] in2_inv = {32{fn[3]}} ^ in2;
  wire [31:0] in1_xor_in2 = in1 ^ in2_inv;
  wire [31:0] _view__adder_out_T_3 = in1 + in2_inv + {31'h0, fn[3]};
  wire        slt = in1[31] == in2[31] ? _view__adder_out_T_3[31] : fn[1] ? in2[31] : in1[31];
  wire [4:0]  shamt = in2[4:0];
  wire        _shout_T = fn == 4'h5;
  wire        _shout_T_1 = fn == 4'hB;
  wire [18:0] _GEN = {in1[5:4], in1[7:6], in1[9:8], in1[11:10], in1[13:12], in1[15:14], in1[17:16], in1[19:18], in1[21:20], in1[23]} & 19'h55555;
  wire [31:0] shin =
    _shout_T | _shout_T_1
      ? in1
      : {in1[0],
         in1[1],
         in1[2],
         in1[3],
         in1[4],
         _GEN[18:15] | {in1[7:6], in1[9:8]} & 4'h5,
         in1[9],
         _GEN[13] | in1[10],
         in1[11],
         in1[12],
         _GEN[10:7] | {in1[15:14], in1[17:16]} & 4'h5,
         in1[17],
         _GEN[5] | in1[18],
         in1[19],
         in1[20],
         {_GEN[2:0], 1'h0} | {in1[23:22], in1[25:24]} & 4'h5,
         in1[25],
         in1[26],
         in1[27],
         in1[28],
         in1[29],
         in1[30],
         in1[31]};
  wire [32:0] _shout_r_T_5 = $signed($signed({fn[3] & shin[31], shin}) >>> shamt);
  wire [31:0] shout_r = _shout_r_T_5[31:0];
  wire [18:0] _GEN_0 = {shout_r[5:4], shout_r[7:6], shout_r[9:8], shout_r[11:10], shout_r[13:12], shout_r[15:14], shout_r[17:16], shout_r[19:18], shout_r[21:20], shout_r[23]} & 19'h55555;
  wire [31:0] shout_l =
    {shout_r[0],
     shout_r[1],
     shout_r[2],
     shout_r[3],
     shout_r[4],
     _GEN_0[18:15] | {shout_r[7:6], shout_r[9:8]} & 4'h5,
     shout_r[9],
     _GEN_0[13] | shout_r[10],
     shout_r[11],
     shout_r[12],
     _GEN_0[10:7] | {shout_r[15:14], shout_r[17:16]} & 4'h5,
     shout_r[17],
     _GEN_0[5] | shout_r[18],
     shout_r[19],
     shout_r[20],
     {_GEN_0[2:0], 1'h0} | {shout_r[23:22], shout_r[25:24]} & 4'h5,
     shout_r[25],
     shout_r[26],
     shout_r[27],
     shout_r[28],
     shout_r[29],
     shout_r[30],
     shout_r[31]};
  wire [31:0] shout = (_shout_T | _shout_T_1 ? shout_r : 32'h0) | (fn == 4'h1 ? shout_l : 32'h0);
  wire        in2_not_zero = |in2;
  wire        _logic_T_4 = fn == 4'h6;
  wire [31:0] logic_0 = (fn == 4'h4 | _logic_T_4 ? in1_xor_in2 : 32'h0) | (_logic_T_4 | fn == 4'h7 ? in1 & in2 : 32'h0);
  wire [31:0] shift_logic = {31'h0, fn > 4'hB & slt} | logic_0 | shout;
  wire [31:0] out_1 = fn == 4'h0 | fn == 4'hA ? _view__adder_out_T_3 : shift_logic;
  assign out = out_1;
  assign adder_out = _view__adder_out_T_3;
  assign cmp_out = fn[0] ^ (fn[3] ? slt : in1_xor_in2 == 32'h0);
endmodule

now:

module ALU(
  input         dw,
  input  [3:0]  fn,
  input  [31:0] in2,
                in1,
  output [31:0] out,
                adder_out,
  output        cmp_out
);

  wire [31:0] in2_inv = {32{fn[3]}} ^ in2;
  wire [31:0] in1_xor_in2 = in1 ^ in2_inv;
  wire [31:0] _view__adder_out_T_3 = in1 + in2_inv + {31'h0, fn[3]};
  wire        slt = in1[31] == in2[31] ? _view__adder_out_T_3[31] : fn[1] ? in2[31] : in1[31];
  wire [4:0]  shamt = in2[4:0];
  wire        _shout_T = fn == 4'h5;
  wire        _shout_T_1 = fn == 4'hB;
  wire [31:0] shin = _shout_T | _shout_T_1 ? in1 : {31'h0, in1[31]};
  wire [32:0] _shout_r_T_5 = $signed($signed({fn[3] & shin[31], shin}) >>> shamt);
  wire [31:0] shout_r = _shout_r_T_5[31:0];
  wire [31:0] shout_l = {31'h0, shout_r[31]};
  wire [31:0] shout = (_shout_T | _shout_T_1 ? shout_r : 32'h0) | (fn == 4'h1 ? shout_l : 32'h0);
  wire        in2_not_zero = |in2;
  wire        _logic_T_4 = fn == 4'h6;
  wire [31:0] logic_0 = (fn == 4'h4 | _logic_T_4 ? in1_xor_in2 : 32'h0) | (_logic_T_4 | fn == 4'h7 ? in1 & in2 : 32'h0);
  wire [31:0] shift_logic = {31'h0, fn > 4'hB & slt} | logic_0 | shout;
  wire [31:0] out_1 = fn == 4'h0 | fn == 4'hA ? _view__adder_out_T_3 : shift_logic;
  assign out = out_1;
  assign adder_out = _view__adder_out_T_3;
  assign cmp_out = fn[0] ^ (fn[3] ? slt : in1_xor_in2 == 32'h0);
endmodule

[sequencer]

I have never used do while before, but I think it always did for at least one time.