Fix mismatch between Chisel and Firrtl on UInt -& UInt #502
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azidar
previously requested changes
Feb 22, 2017
| val subout = Output(UInt(32.W)) | ||
| val addampout = Output(UInt(33.W)) | ||
| val subampout = Output(UInt(33.W)) | ||
| //val subampout = Output(UInt(32.W)) |
aswaterman
approved these changes
Feb 24, 2017
Fixes #501. Also added UIntOps test.
jackkoenig
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I removed the comments (and removed the couple of extra lines that were working around #500 which was merged in the meantime) |
aswaterman
dismissed
azidar’s stale review
[review comments have been addressed]
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Fixes #501. Also added UIntOps test.