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Fix getWidth on empty Vecs; add test #561

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Mar 24, 2017
Merged

Fix getWidth on empty Vecs; add test #561

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2 changes: 1 addition & 1 deletion chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ sealed abstract class Aggregate extends Data {
*/
def getElements: Seq[Data]

private[core] def width: Width = getElements.map(_.width).reduce(_ + _)
private[core] def width: Width = getElements.map(_.width).foldLeft(0.W)(_ + _)
private[core] def legacyConnect(that: Data)(implicit sourceInfo: SourceInfo): Unit =
pushCommand(BulkConnect(sourceInfo, this.lref, that.lref))

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9 changes: 9 additions & 0 deletions src/test/scala/chiselTests/Vec.scala
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Expand Up @@ -134,6 +134,11 @@ class OneBitUnitRegVecTester extends BasicTester {
stop()
}

class ZeroEntryVecTester extends BasicTester {
require(Vec(0, Bool()).getWidth == 0)
stop()
}

class VecSpec extends ChiselPropSpec {
// Disable shrinking on error.
implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
Expand Down Expand Up @@ -187,4 +192,8 @@ class VecSpec extends ChiselPropSpec {
property("A Reg of a Vec of a single 1 bit element should compile and work") {
assertTesterPasses{ new OneBitUnitRegVecTester }
}

property("A Vec with zero entries should compile and have zero width") {
assertTesterPasses{ new ZeroEntryVecTester }
}
}