[Issue riscv-non-isa#33] rv32si/ma_fetch fix

debs-sifive · Feb 6, 2019 · 395bdd0 · 395bdd0
1 parent 8dac5e5
commit 395bdd0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/riscv-test-suite/rv32si/rv64si/ma_fetch.S b/riscv-test-suite/rv32si/rv64si/ma_fetch.S
@@ -199,7 +199,7 @@ stvec_handler:
   bne a0, t0, fail
 1:
 
-  addi a1, a1, 12
+  addi a1, a1, 8
   csrw sepc, a1
   sret