[Issue riscv-non-isa#33] rv32si/ma_fetch fix

debs-sifive · Feb 6, 2019 · fb097c0 · fb097c0
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diff --git a/ChangeLog b/ChangeLog
@@ -1,3 +1,10 @@
+2019-02-05 Deborah Soung <debs@sifive.com>
+    * [Issue #33] rv32si/ma_fetch fix
+
+2019-02-01 Lee Moore <moore@imperas.com>
+    * updated Infrastructure macros to support non-volatile registers
+    * updated riscvOVPsim
+
 2019-01-29 Deborah Soung <debs@sifive.com>
     * Added Rocket Chip generated cores as a target
         * riscv-target/rocket/compliance_io.h created

diff --git a/doc/ChangeLog b/doc/ChangeLog
@@ -1,3 +1,6 @@
+2019-02-05  Deborah Soung  <debs@sifive.com>
+	* README.adoc: Update documentation for rocket chip as target (fixed rv32si/ma_fetch.S).
+
 2019-01-29  Deborah Soung  <debs@sifive.com>
 	* README.adoc: Documentation for rocket chip as target.
 

diff --git a/doc/README.adoc b/doc/README.adoc
@@ -317,8 +317,8 @@ For tracing the test the following  macros are defined in `riscv-target/riscvOVP
 [source,make]
 ----
 RVTEST_IO_INIT
-RVTEST_IO_WRITE_STR(_STR)
-RVTEST_IO_ASSERT_GPR_EQ(_R, _I)
+RVTEST_IO_WRITE_STR(_SP, _STR)
+RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
 ----
 
 An example of a test that uses the tracing macros is `riscv-test-suite/rv32i/ISA/src/I-IO.S`.
@@ -361,7 +361,7 @@ Additional environment variables:
 
 Before running the compliance test, make sure that the correct emulator is built, following the link:https://github.com/freechipsproject/rocket-chip#emulator[instructions in the Rocket Chip repository].
 
-**Note**: Rocket Chip's `DefaultRV32Config` is currently failing the following tests — link:https://github.com/riscv/riscv-compliance/issues/31[rv32i/I-MISALIGN_JMP-01.S], link:https://github.com/riscv/riscv-compliance/issues/32[rv32mi/breakpoint.S], link:https://github.com/riscv/riscv-compliance/issues/33[rv32si/ma_fetch.S].
+**Note**: Rocket Chip's `DefaultRV32Config` is currently failing the following tests — link:https://github.com/riscv/riscv-compliance/issues/31[rv32i/I-MISALIGN_JMP-01.S], link:https://github.com/riscv/riscv-compliance/issues/32[rv32mi/breakpoint.S].
 
 === SiFive Freedom Unleashed 540 board (tbd)
 

diff --git a/riscv-ovpsim/ChangeLog.md b/riscv-ovpsim/ChangeLog.md
@@ -3,12 +3,169 @@ riscvOVPsim Fixed Platform Kit Change Log
 
 # Changes since last release
 
-- Added ChangeLog.md to track changes
+RISCV Processor Model
+-------------------------------------------------------------------------------
+- The model now supports save and restore.
+- Field mstatus.MPP has been changed from WLRL to WARL in accordance with
+  version 1.11 of the Privileged Specification). When written with an illegal
+  value, the previous legal value is preserved.
+- RMM rounding mode is now fully implemented for all operations.
+- A bug has been fixed in which some floating point convert operations were not
+  causing Illegal Instruction exceptions when rounding modes 5 and 6 were
+  specified in the instruction.
+- A bug has been fixed which could cause permissions for locked PMP regions to
+  be ignored in Machine mode in some cases.
+- A bug has been fixed which would prevent instruction access faults being
+  raised in some circumstances for instructions that straddle PMP region
+  boundaries.
+- A new parameter PMP_grain allows the grain size (G) of PMP regions to be
+  specified. For example, a value of 3 indicates that the smallest implemented
+  PMP region size is 32 bytes.
 
-# Changes for v20180607
+###############################################################################
+##                                                                           ##
+## Date 2018-November-14                                                     ##
+##                                                                           ##
+## Release 20181114.0                                                        ##
+##                                                                           ##
+###############################################################################
 
-- initial release
+RISCV Processor Model
+-------------------------------------------------------------------------------
+- A bug has been fixed which allowed User mode accesses to unimplemented
+  hardware performance registers irrespective of the settings in the counter
+  enable registers.
+- Instruction address misaligned faults are now taken on the branch or jump
+  instruction instead of the target instruction.
+- A bug has been fixed in which RV64 instructions like sraiw with shifts >= 32
+  bits (e.g. sraiw a2,a2,0x20) did not cause an exception.
+- A bug has been fixed in which compressed instructions with shifts >= 32 bits
+  (e.g. srai a2,a2,0x20) did not cause an exception when RV64I is absent or
+  disabled.
+- Decode for compressed instructions c.addi4spn, c.addi16sp, c.lui, c.jr,
+  c.addiw, c.lwsp and c.ldsp has been corrected to properly handle reserved
+  cases.
+- A bug has been fixed in which the source value of fmv.s instructions was not
+  being checked as NaN-boxed.
+- A bug has been fixed which caused sedeleg and sideleg registers to be present
+  when user-level interrupts were present and supervisor mode was absent. These
+  registers should be present only if both supervisor mode and user-level
+  interrupts are present.
 
----
+RISCV Processor Model Feature Usage Examples
+-------------------------------------------------------------------------------
+- Two examples are provided to show the use of features of the RISCV model. these
+  are provided under Examples/Models/Processors/Feature_Usage as
+  RISCV_SignatureDump
+    Shows the use of the extension library to control the generation of a signature
+    file.
+  RISCV_CustomInstructionFlow
+    Shows how to extend a RISCV processor with a custom instruction.
 
-This is the riscvOVPsim/Changelog.md  
+###############################################################################
+##                                                                           ##
+## Date 2018-August-03                                                       ##
+##                                                                           ##
+## Release 20180716.2                                                        ##
+##                                                                           ##
+###############################################################################
+
+###############################################################################
+##                                                                           ##
+## Date 2018-July-16                                                         ##
+##                                                                           ##
+## Release 20180716.0                                                        ##
+##                                                                           ##
+###############################################################################
+
+RISCV Processor Model
+-------------------------------------------------------------------------------
+- The RISCV processor model has been changed to set the default initial PC at 
+  simulation start to the value indicated by the processor model's reset_address
+  parameter. Previously the default start address was 0x0.
+  NOTE: The --startaddress command line argument or the start address from an 
+  ELF file that is loaded will override this value.
+  NOTE: The default value for the reset_address can vary by variant, since this
+  is defined to be an implementation dependent value by the RISCV specification.
+  See the Model Specific Information document to see what value is implemented 
+  for a specific variant.
+- A new SiFive variant 'U54MC' has been added, which implements a cluster of
+  U54 harts. By default 4 harts are implemented, which may be overridden using
+  the numHarts parameter which allows values from 1 to 32.
+
+###############################################################################
+##                                                                           ##
+## Date 2018-March-12                                                        ##
+##                                                                           ##
+## Release 20180221.1                                                        ##
+##                                                                           ##
+###############################################################################
+
+###############################################################################
+##                                                                           ##
+## Date 2018-February-21                                                     ##
+##                                                                           ##
+## Release 20180221.0                                                        ##
+##                                                                           ##
+###############################################################################
+
+RISCV Processor Model
+-------------------------------------------------------------------------------
+- The model has been extensively rewritten to implement privilege levels and
+  state consistent with Privileged Architecture version 1.10, including virtual
+  memory and physical memory protection registers.
+- An intercept (extension) library can be loaded and a SignatureFile parameter 
+  specified to set the file into which a signature, compatible with that
+  generated by the Spike simulator, will be written. Load the intercept library
+  by adding 
+    --extlib riscv.ovpworld.org/intercept/spike/1.0
+  to the command line.
+- The riscv processor models for vendors Andes, SiFive and Microsemi have been 
+  renamed
+  To see the variants for a specific vendor you should now use
+    iss.exe --showvariants --processorvendor riscv.ovpworld.org     --processorname riscv
+    iss.exe --showvariants --processorvendor andes.ovpworld.org     --processorname riscv
+    iss.exe --showvariants --processorvendor sifive.ovpworld.org    --processorname riscv
+    iss.exe --showvariants --processorvendor microsemi.ovpworld.org --processorname riscv
+
+###############################################################################
+##                                                                           ##
+## Date 2017-September-19                                                    ##
+##                                                                           ##
+## Release 20170919.0                                                        ##
+##                                                                           ##
+###############################################################################
+
+RISC-V Processor Models
+-------------------------------------------------------------------------------
+This is the first release of our collection of RISC-V models. There is a generic
+model that implements the RISC-V ISA variants and there are vendor specific
+cores from Andes, SiFive, and Microsemi.
+
+To see the available processor models use:
+    iss.exe --showlibraryprocessors
+and to see the specific variants these contain use:
+    iss.exe --showvariants --processorname riscv
+    iss.exe --showvariants --processorname andes_riscv
+    iss.exe --showvariants --processorname sifive_riscv
+    iss.exe --showvariants --processorname microsemi_riscv
+
+###############################################################################
+##                                                                           ##
+## Date 2017-May-12                                                          ##
+##                                                                           ##
+## Release 20170511.0                                                        ##
+##                                                                           ##
+###############################################################################
+
+RISCV Processor Model
+-------------------------------------------------------------------------------
+- The model supporting variants RV32G, RV32I, RV64G and RV64I is released.
+
+###############################################################################
+##                                                                           ##
+## Date 2017-February-01                                                     ##
+##                                                                           ##
+## Release 20170201.0                                                        ##
+##                                                                           ##
+###############################################################################
diff --git a/riscv-ovpsim/LICENSE.pdf b/riscv-ovpsim/LICENSE.pdf
diff --git a/riscv-ovpsim/README.md b/riscv-ovpsim/README.md
@@ -4,8 +4,8 @@ A Complete, Fully Functional, Configurable RISC-V Simulator
 ===
 
 Author: Imperas Software, Ltd., using OVP Open Standard APIs  
-Date   : 16 Nov 2018 
-Version: 20181126.0  
+Date   : 31 Jan 2019 
+Version: 20190131.0  
 License: Model source included under Apache 2.0 open source license  
 License: Simulator riscvOVPsim licensed under Open Virtual Platforms (OVP) Fixed Platform Kits license  
 RISC-V Specifications currently supported:

diff --git a/riscv-ovpsim/bin/Linux64/riscvOVPsim.exe b/riscv-ovpsim/bin/Linux64/riscvOVPsim.exe
diff --git a/riscv-ovpsim/bin/Windows64/riscv64-unknown-elf-gdb.exe b/riscv-ovpsim/bin/Windows64/riscv64-unknown-elf-gdb.exe
diff --git a/riscv-ovpsim/bin/Windows64/riscvOVPsim.exe b/riscv-ovpsim/bin/Windows64/riscvOVPsim.exe
diff --git a/riscv-ovpsim/doc/riscvOVPsim_User_Guide.pdf b/riscv-ovpsim/doc/riscvOVPsim_User_Guide.pdf
diff --git a/riscv-ovpsim/source/riscvAttrs.c b/riscv-ovpsim/source/riscvAttrs.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ * Copyright (c) 2005-2019 Imperas Software Ltd., www.imperas.com
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.
@@ -54,6 +54,14 @@ const vmiIASAttr modelAttrs = {
     .cpuSize            = sizeof(riscv),
     .blockStateSize     = sizeof(riscvBlockState),
 
+    ////////////////////////////////////////////////////////////////////////
+    // SAVE/RESTORE ROUTINES
+    ////////////////////////////////////////////////////////////////////////
+
+    .saveCB             = riscvSaveState,
+    .restoreCB          = riscvRestoreState,
+    .srVersion          = 0,
+
     ////////////////////////////////////////////////////////////////////////
     // CONSTRUCTOR/DESTRUCTOR ROUTINES
     ////////////////////////////////////////////////////////////////////////

diff --git a/riscv-ovpsim/source/riscvBlockState.h b/riscv-ovpsim/source/riscvBlockState.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ * Copyright (c) 2005-2019 Imperas Software Ltd., www.imperas.com
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.

diff --git a/riscv-ovpsim/source/riscvBus.c b/riscv-ovpsim/source/riscvBus.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ * Copyright (c) 2005-2019 Imperas Software Ltd., www.imperas.com
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.

diff --git a/riscv-ovpsim/source/riscvBus.h b/riscv-ovpsim/source/riscvBus.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2005-2018 Imperas Software Ltd., www.imperas.com
+ * Copyright (c) 2005-2019 Imperas Software Ltd., www.imperas.com
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
  * you may not use this file except in compliance with the License.