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Assertion failed 'isValidVectorElemsizeFloat(size)' during 'Generate code' #91214
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arch-arm64
area-CodeGen-coreclr
CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
os-windows
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CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
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Aug 28, 2023
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue Details// Found by Antigen
using System;
using System.Collections.Generic;
using System.Runtime.CompilerServices;
using System.Runtime.Intrinsics;
using System.Runtime.Intrinsics.Arm;
using System.Numerics;
public class TestClass
{
public struct S1
{
}
public struct S2
{
}
public struct S3
{
public struct S3_D1_F1
{
}
public struct S3_D1_F4
{
}
public Vector3 v3_5;
public bool bool_6;
}
public struct S4
{
}
public struct S5
{
}
static Vector64<ulong> s_v64_ulong_31 = Vector64.Create((ulong)1);
static S3.S3_D1_F1 s_s3_s3_d1_f1_61 = new S3.S3_D1_F1();
static S3 s_s3_63 = new S3();
Vector64<ulong> v64_ulong_87 = Vector64.Create((ulong)5);
static int s_loopInvariant = 6;
public S3 Method2(ref S3.S3_D1_F1 p_s3_s3_d1_f1_162)
{
unchecked
{
S1 s1_179 = new S1();
S2 s2_180 = new S2();
S3.S3_D1_F4 s3_s3_d1_f4_183 = new S3.S3_D1_F4();
S4 s4_185 = new S4();
S5 s5_186 = new S5();
int __loopvar17 = s_loopInvariant + 9;
Log("s1_179", s1_179);
Log("s2_180", s2_180);
Log("s3_s3_d1_f", s3_s3_d1_f4_183);
Log("s4_185", s4_185);
Log("s5_186", s5_186);
return s_s3_63;
}
}
public void Method0()
{
unchecked
{
S3 s3_221 = new S3();
S3 s3_222 = s3_221;
s_v64_ulong_31 = Vector64.ConditionalSelect(v64_ulong_87, v64_ulong_87 *= 15|4, s_v64_ulong_31 | (v64_ulong_87 *= Vector64<ulong>.Zero)^ (v64_ulong_87 += s_v64_ulong_31));
s3_222 = Method2(ref s_s3_s3_d1_f1_61);
Log("s3_222.v3_", s3_222.v3_5);
return;
}
}
public static void Main(string[] args)
{
new TestClass().Method0();
}
[MethodImpl(MethodImplOptions.NoInlining)]
public static void Log(string varName, object varValue)
{} }
/*
Environment:
set COMPlus_TieredCompilation=0
Assert failure(PID 3508 [0x00000db4], Thread: 11984 [0x2ed0]): Assertion failed 'isValidVectorElemsizeFloat(size)' in 'TestClass:Method0():this' during 'Generate code' (IL size 148; hash 0x46e9aa75; FullOpts)
File: D:\a\_work\1\s\src\coreclr\jit\emitarm64.cpp Line: 4225
Image: e:\kpathak\CORE_ROOT\corerun.exe
*/
|
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Aug 28, 2023
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Locals with SIMD12 fields will never match the ABI when they end up as multireg returns, so these should always be DNER'd. Fix dotnet#91214
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Locals with SIMD12 fields will span multiple registers when they end up as multireg returns, so these should always be DNER'd. Fix #91214
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Locals with SIMD12 fields will never match the ABI when they end up as multireg returns, so these should always be DNER'd. Fix dotnet#91214
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* JIT: DNER multiregs with SIMD12s Locals with SIMD12 fields will never match the ABI when they end up as multireg returns, so these should always be DNER'd. Fix #91214 * Fix test build
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Labels
arch-arm64
area-CodeGen-coreclr
CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI
os-windows
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