[Arm64] Support table-driven code generation for scalar intrinsics #208
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Dotnet-GitSync-Bot
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area-CodeGen-coreclr
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@CarolEidt @tannergooding PTAL cc @dotnet/jit-contrib |
… between table-driven and special intrinsics in jit/hwintrinsiccodegenarm64.cpp
sandreenko
approved these changes
Nov 27, 2019
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| assert(op2 == nullptr); | ||
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| GenTreeArgList* list = op1->AsArgList(); |
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Is it possible that somebody uses GenTreeArgList to encode 2 args form?
GT_LIST
+--* arg1
\--* GT_LIST
+--* arg2
\--* nullptr
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This should not happen. The list form is supposed to be used only for more than 2 args. And hopefully not for long...
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Welcome to the new repo @mikedn 😃
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Kind of late to the party... The removal of node->GetNumUses();
node->GetOp(1); |
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I have to delete/re-create my fork of the runtime repo - I will re-open this PR after that. |
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Motivation 1: To support table-driven approach during code generation of "simple" scalar intrinsics (the ones that don't require non-trivial instruction lookup or moving the values between operand registers and destination register).
Motivation 2: To support special (non table-driven) codegen of intrinsics with 3 operands (e.g.
BitwiseSelect).When I implemented these logics for scalar intrinsics and 3 operands intrinsics I found that functions
CodeGen::genHWIntrinsicandCodeGen::genSpecialIntrinsichave at least 50% of the identical code so I moved the shared preparatory logic (that looks up intrinsic ID and category, the corresponding operand nodes, and base type) to a separate classHWIntrinsic.This way I could remove special codegen for
NI_ArmBase_LeadingZeroCountNI_ArmBase_Arm64_LeadingSignCountNI_ArmBase_Arm64_LeadingZeroCount.