Generate proper DWARF reg num for ARM32 #57443
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After introduction of VFP-v3 ARM S0-S31 no longer can be generated using LLVM because numbering of registers to start from 256 and only D0-D31 are used. So this change encode S0 as D0, S2 as D1, etc. Also use reg nums for DXX registers. This change fix generation of CFI codes, which trigger issue with generation of DWARF using LLVM in NativeAOT See https://developer.arm.com/documentation/ihi0040/c/?lang=en#dwarf-register-names See dotnet/runtimelab#1388
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Tagging subscribers to this area: @JulieLeeMSFT Issue DetailsAfter introduction of VFP-v3 ARM S0-S31 no longer can be generated using LLVM because numbering of registers to start from 256 and only D0-D31 are used.
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@kunalspathak please review the community PR. |
Note that this is NativeAOT specific code currently. |
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LGTM - with 1 refactoring suggestion. |
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@kunalspathak what suggestion? I did not see any of them. |
src/coreclr/jit/unwind.cpp
Outdated
| @@ -187,7 +187,12 @@ void Compiler::unwindPushPopMaskCFI(regMaskTP regMask, bool isFloat) | |||
| regMaskTP regBit = isFloat ? genRegMask(REG_FP_FIRST) : 1; | |||
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| for (regNumber regNum = isFloat ? REG_FP_FIRST : REG_FIRST; regNum < REG_COUNT; | |||
| regNum = REG_NEXT(regNum), regBit <<= 1) | |||
| #if TARGET_ARM | |||
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For better readability, I would rewrite this to. I would add a short comment for why we need to do special case for ARM.
regNumber regNum = isFloat ? REG_FP_FIRST : REG_FIRST;
for (; regNum < REG_COUNT;)
{
#if TARGET_ARM
regNum = isFloat ? REG_NEXT(REG_NEXT(regNum)) : REG_NEXT(regNum);
regBit <<= isFloat ? 2 : 1;
#else
regNum = REG_NEXT(regNum);
regBit <<= 1;
#endregion
...
...
}
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Aug 16, 2021
…information # By dotnet-maestro[bot] (4) and others # Via GitHub * origin/main: (58 commits) Localized file check-in by OneLocBuild Task (dotnet#57384) [debugger][wasm] Support DebuggerProxyAttribute (dotnet#56872) Account for type mismatch of `FIELD_LIST` members in LSRA (dotnet#57450) Qualify `sorted_table` allocation with `nothrow` (dotnet#57467) Rename transport packages to follow convention (dotnet#57504) Generate proper DWARF reg num for ARM32 (dotnet#57443) Enable System.Linq.Queryable and disable dotnet#50712 (dotnet#57464) Mark individual tests for 51211 (dotnet#57463) Fix Length for ReadOnlySequence created out of sliced Memory owned by MemoryManager (dotnet#57479) Add JsonConverter.Write/ReadAsPropertyName APIs (dotnet#57302) Remove workaround for dotnet/sdk#19482 (dotnet#57453) Do not drain HttpContentReadStream if the connection is disposed (dotnet#57287) [mono] Fix a few corner case overflow operations (dotnet#57407) make use of ports in SPN optional (dotnet#57159) Fixed H/3 stress server after the last Kestrel change (dotnet#57356) disable a failing stress test. (dotnet#57473) Eliminate temporary byte array allocations in the static constructor of `IPAddress`. (dotnet#57397) Update dependencies from https://github.com/dotnet/emsdk build 20210815.1 (dotnet#57447) [main] Update dependencies from mono/linker (dotnet#57344) Improve serializer performance (dotnet#57327) ... # Conflicts: # src/mono/wasm/debugger/BrowserDebugProxy/MemberReferenceResolver.cs # src/mono/wasm/debugger/BrowserDebugProxy/MonoProxy.cs # src/mono/wasm/debugger/BrowserDebugProxy/MonoSDBHelper.cs
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After introduction of VFP-v3 ARM S0-S31 no longer can be generated using LLVM because numbering of registers to start from 256 and only D0-D31 are used.
So this change encode S0 as D0, S2 as D1, etc. Also use reg nums for DXX registers.
This change fix generation of CFI codes,
which trigger issue with generation of DWARF using LLVM in NativeAOT
See https://developer.arm.com/documentation/ihi0040/c/?lang=en#dwarf-register-names
See dotnet/runtimelab#1388