- Remove NYIs/control flow preventing code splitting on ARM64.
- Update emitter::emitIns_J() to keep jumps between hot/cold sections
long.
- Update emitter::emitOutputLJ() to emit long jumps for both
conditional and unconditional branches between hot/cold sections, and
report relocations to the runtime.
- Update long ldr pseudoinstruction to instead use ld1 instruction
when loading 16-byte constants into vector registers; ldr
implementation temporarily loads the constant into a general integer
register, which does not support 16-byte values.

- Remove NYIs/control flow preventing code splitting on ARM64.
- Update emitter::emitIns_J() to keep jumps between hot/cold sections
long.
- Update emitter::emitOutputLJ() to emit long jumps for both
conditional and unconditional branches between hot/cold sections, and
report relocations to the runtime.
- Update long ldr pseudoinstruction to instead use ld1 instruction
when loading 16-byte constants into vector registers; ldr
implementation temporarily loads the constant into a general integer
register, which does not support 16-byte values.

This commit contains fixes for various bugs exposed by enabling fake
hot/cold splitting on ARM64:
- Branches between hot/cold sections are now always long.
- The pseudoinstruction for loading a constant from the cold section
did not support loading 16-byte data into vector registers, as it
temporarily loaded the constant into an 8-byte integer register. Now,
16-byte constants are loaded directly into vector registers via an
`ld1` instruction.
- Tests involving loading 16-byte constants exposed the data section
is not always aligned to its largest constant. Now, the data section
is always aligned to `emitConsDsc.alignment` when calling `eeAllocMem`.
- Asserts/NYIs blocking hot/cold splitting on ARM64 have been removed.

Fake hot/cold splitting requires we fake unwind info by treating each
split function as one hot section. A more architecture-agnostic
approach for this has been applied.

This commit contains fixes for various bugs exposed by enabling fake
hot/cold splitting on ARM64:
- Branches between hot/cold sections are now always long.
- The pseudoinstruction for loading a constant from the cold section
did not support loading 16-byte data into vector registers, as it
temporarily loaded the constant into an 8-byte integer register. Now,
16-byte constants are loaded directly into vector registers via an
`ld1` instruction.
- Tests involving loading 16-byte constants exposed the data section
is not always aligned to its largest constant. Now, the data section
is always aligned to `emitConsDsc.alignment` when calling `eeAllocMem`.
- Asserts/NYIs blocking hot/cold splitting on ARM64 have been removed.

Fake hot/cold splitting requires we fake unwind info by treating each
split function as one hot section. A more architecture-agnostic
approach for this has been applied.

…d/runtime into code-splitting-arm

The newly-introduced `emitRemoveJumpToNextInst` optimization caused
a regression when hot/cold-splitting, where jumps from the last hot
instruction to the first cold instruction were erroneously removed.
This is fixed by disabling the `isRemovableJmpCandidate` flag for
branches between hot/cold sections.

On an unrelated note, a JIT dump message has been added to indicate
stress-splitting is occurring.

…d/runtime into code-splitting-arm

To facilitate generating unwind info, fake-splitting now places the
read-only data section after the cold section. This allows the
hot/cold code sections to be truly contiguous.