Enable fake hot/cold splitting on ARM64 #70708
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- Remove NYIs/control flow preventing code splitting on ARM64. - Update emitter::emitIns_J() to keep jumps between hot/cold sections long. - Update emitter::emitOutputLJ() to emit long jumps for both conditional and unconditional branches between hot/cold sections, and report relocations to the runtime. - Update long ldr pseudoinstruction to instead use ld1 instruction when loading 16-byte constants into vector registers; ldr implementation temporarily loads the constant into a general integer register, which does not support 16-byte values.
- Remove NYIs/control flow preventing code splitting on ARM64. - Update emitter::emitIns_J() to keep jumps between hot/cold sections long. - Update emitter::emitOutputLJ() to emit long jumps for both conditional and unconditional branches between hot/cold sections, and report relocations to the runtime. - Update long ldr pseudoinstruction to instead use ld1 instruction when loading 16-byte constants into vector registers; ldr implementation temporarily loads the constant into a general integer register, which does not support 16-byte values.
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsThis PR enables fake hot/cold splitting on ARM64 via
Fake hot/cold splitting requires we fake unwind info by treating each split function as one hot section. A more architecture-agnostic approach for this has been applied. However, unwind info generated for cold sections has yet to be tested, as this depends on VM support for hot/cold splitting.
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/azp run runtime-jit-experimental |
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Azure Pipelines successfully started running 1 pipeline(s). |
This commit contains fixes for various bugs exposed by enabling fake hot/cold splitting on ARM64: - Branches between hot/cold sections are now always long. - The pseudoinstruction for loading a constant from the cold section did not support loading 16-byte data into vector registers, as it temporarily loaded the constant into an 8-byte integer register. Now, 16-byte constants are loaded directly into vector registers via an `ld1` instruction. - Tests involving loading 16-byte constants exposed the data section is not always aligned to its largest constant. Now, the data section is always aligned to `emitConsDsc.alignment` when calling `eeAllocMem`. - Asserts/NYIs blocking hot/cold splitting on ARM64 have been removed. Fake hot/cold splitting requires we fake unwind info by treating each split function as one hot section. A more architecture-agnostic approach for this has been applied.
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/azp run runtime-jit-experimental |
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Azure Pipelines successfully started running 1 pipeline(s). |
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Closing to prevent re-running checks. |
This commit contains fixes for various bugs exposed by enabling fake hot/cold splitting on ARM64: - Branches between hot/cold sections are now always long. - The pseudoinstruction for loading a constant from the cold section did not support loading 16-byte data into vector registers, as it temporarily loaded the constant into an 8-byte integer register. Now, 16-byte constants are loaded directly into vector registers via an `ld1` instruction. - Tests involving loading 16-byte constants exposed the data section is not always aligned to its largest constant. Now, the data section is always aligned to `emitConsDsc.alignment` when calling `eeAllocMem`. - Asserts/NYIs blocking hot/cold splitting on ARM64 have been removed. Fake hot/cold splitting requires we fake unwind info by treating each split function as one hot section. A more architecture-agnostic approach for this has been applied.
…d/runtime into code-splitting-arm
The newly-introduced `emitRemoveJumpToNextInst` optimization caused a regression when hot/cold-splitting, where jumps from the last hot instruction to the first cold instruction were erroneously removed. This is fixed by disabling the `isRemovableJmpCandidate` flag for branches between hot/cold sections. On an unrelated note, a JIT dump message has been added to indicate stress-splitting is occurring.
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I've added commits that update the fake-splitting implementation to place the read-only data section after the cold section on ARM64. This allows the hot/cold sections to be truly contiguous -- previously, the read-only data section was placed after the hot section. This placement should better facilitate generating fake unwind info, thus fixing stack walks when fake-splitting. |
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/azp run runtime-jit-experimental |
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I realized my implementation for aligning the data section when fake-splitting is overzealous, and simply tweaking the current implementation to align to @BruceForstall PTAL. I noticed |
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/azp run runtime-jit-experimental Edit: Checks didn't trigger for some reason... I'll wait to restart them after addressing feedback. |
Looks like a (bad) recent regression. I opened #71023. |
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/azp run runtime |
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To facilitate generating unwind info, fake-splitting now places the read-only data section after the cold section. This allows the hot/cold code sections to be truly contiguous.
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@BruceForstall PTAL at |
I like this direction. Unfortunately, and I apologize, this change is going to clash with my change #71044. Can we wait until that is merged (today), and then review this? You'll need to pick up its changes into this. |
No worries! |
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@BruceForstall I merged your changes from #71044 in, and added a guard to disable splitting on LoongArch64. Thanks for the ARM64 alignment work -- I recall hitting some related asserts when trying to load 16-byte constants a few weeks ago... |
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/azp run runtime-jit-experimental |
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Azure Pipelines successfully started running 1 pipeline(s). |
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Merging this PR for now. Will submit a follow-up PR disabling hot/cold splitting when |
This PR enables fake hot/cold splitting on ARM64 via
COMPlus_JitFakeProcedureSplitting, and fixes various bugs exposed by testing with fake-splitting:ld1instruction.emitConsDsc.alignmentwhen callingeeAllocMem.Fake hot/cold splitting requires we fake unwind info by treating each split function as one hot section. A more architecture-agnostic approach for this has been applied. However, unwind info generated for cold sections has yet to be tested, as this depends on VM support for hot/cold splitting.