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Adding support for Vector512 bitwise operations: And, AndNot, Or, OnesComplement, and Xor #83354
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Note regarding the This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, to please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change. |
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch, @kunalspathak |
src/coreclr/jit/emitxarch.h
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if (IsRexW1Instruction(ins)) | ||
{ | ||
return true; | ||
} | ||
else if (IsRexWIGInstruction(ins) || IsRexW0Instruction(ins)) | ||
{ | ||
// TODO: Make this a simple assert once all instructions are annotated | ||
return false; | ||
} | ||
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I plan on covering this TODO
in a follow-up PR (notably will be the "next" thing I do).
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Do we have any systematic way to improve upon the INS_has_wbit
flag and the opcode extension bit flag?
I agree that we can move the opcode extension bit into the instruction table, but the TakesRexWBit
check is still pretty complicated and requires a lot of contextual information.
If we eventually move everything to checks on instrDesc
instead of ins
, we probably can simplify this quite a bit. That is later down the road though.
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I can take a look as part of this. It would indeed be nicer/simpler to be able to handle this "everywhere".
I imagine many of the GPR instructions need something like REX_WX
bit that indicates its 0 or 1 based on the EA_ATTR size or alternatively some way to split the instructions between D
and Q
versions.
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Have a prototype of tracking the REX.W bit stuff for SIMD via #83473. It should be extensible to GPR as well
src/coreclr/jit/compiler.cpp
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// We can't use !DoJitStressEvexEncoding() yet because opts.compSupportsISA hasn't | ||
// been set yet as that's what we're trying to set here | ||
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if (!JitConfig.JitForceEVEXEncoding() && !JitConfig.JitStressEvexEncoding() && | ||
!instructionSetFlags.HasInstructionSet(InstructionSet_AVX512F_VL)) |
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This was previously !DoJitStressEvexEncoding()
and was preventing just JitStressEvexEncoding
from working since the support check for AVX512F_VL
would always fail.
@@ -632,7 +632,7 @@ static bool isSupportedBaseType(NamedIntrinsic intrinsic, CorInfoType baseJitTyp | |||
#ifdef DEBUG | |||
CORINFO_InstructionSet isa = HWIntrinsicInfo::lookupIsa(intrinsic); | |||
#ifdef TARGET_XARCH | |||
assert((isa == InstructionSet_Vector256) || (isa == InstructionSet_Vector128)); | |||
assert((isa == InstructionSet_Vector512) || (isa == InstructionSet_Vector256) || (isa == InstructionSet_Vector128)); |
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This assert was missing and so we weren't actually testing any InstructionSet_Vector512 paths yet.
#if defined(TARGET_ARM64) | ||
if ((simdSize != 8) && (simdSize != 16)) | ||
#elif defined(TARGET_XARCH) | ||
if ((simdSize != 16) && (simdSize != 32) && (simdSize != 64)) |
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Same for this check against simdSize != 64
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CC. @dotnet/jit-contrib, @dotnet/avx512-contrib |
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Rebase to pickup the fix for #83298 |
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namespace JIT.HardwareIntrinsics.X86._Avx512F | ||
{ | ||
public static partial class Program |
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Is this how these tests are organized or it's a dead code?
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Its a stub file that all the generated test projects have at the moment. We could probably remove it, but it's part of the existing "template" so I copied it here as well.
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LGTM, assuming all tests your changed aren't some outerloop that will break later 🙂
Also I assume for now we don't constant fold any of this ops you just added, right? (presumably, extremely low priority)
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They run as part of the
Right, we'll end up going back and adding the constant folding support around the time it gets enabled automatically. Just rebased onto main to pick up a CI fix so I can merge green. |
coreclr linux x64 Debug failures are #83482 Failures in general can be seen to also exist in last scheduled run: https://dev.azure.com/dnceng-public/public/_build/results?buildId=206663&view=ms.vss-test-web.build-test-results-tab&runId=3838833&paneView=debug |
This makes progress towards #80814 and #73604
This is dependent on #83402