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Add Arm64 encodings for IF_SVE_CY_3A and IF_SVE_CY_3B group #96992

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merged 3 commits into from
Jan 17, 2024
Merged

Add Arm64 encodings for IF_SVE_CY_3A and IF_SVE_CY_3B group #96992

merged 3 commits into from
Jan 17, 2024

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SwapnilGaikwad
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This group emits various compare instructions.

This clr output matches the one from capstone.

cmpeq p15.b, p0/z, z31.b, #8
cmpge p11.h, p7/z, z21.h, #1
cmpgt p10.s, p1/z, z18.s, #4
cmple p8.d, p6/z, z11.d, #15
cmplt p7.b, p2/z, z8.b, #-16
cmpne p0.h, p5/z, z0.h, #-14
cmphi p15.b, p7/z, z19.b, #0
cmphs p11.h, p1/z, z0.h, #0x24
cmplo p8.s, p5/z, z21.s, #0x40
cmpls p0.d, p3/z, z9.d, #0x7F

Contribute towards #94549.

@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jan 15, 2024
@ghost ghost added the community-contribution Indicates that the PR has been added by a community member label Jan 15, 2024
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Issue Details

This group emits various compare instructions.

This clr output matches the one from capstone.

cmpeq p15.b, p0/z, z31.b, #8
cmpge p11.h, p7/z, z21.h, #1
cmpgt p10.s, p1/z, z18.s, #4
cmple p8.d, p6/z, z11.d, #15
cmplt p7.b, p2/z, z8.b, #-16
cmpne p0.h, p5/z, z0.h, #-14
cmphi p15.b, p7/z, z19.b, #0
cmphs p11.h, p1/z, z0.h, #0x24
cmplo p8.s, p5/z, z21.s, #0x40
cmpls p0.d, p3/z, z9.d, #0x7F

Contribute towards #94549.

Author: SwapnilGaikwad
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area-CodeGen-coreclr
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This was referenced Jan 15, 2024
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a74nh commented Jan 17, 2024

@kunalspathak

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Everything else LGTM.

src/coreclr/jit/emitarm64.cpp
case IF_SVE_CY_3A: // ........xx.iiiii ...gggnnnnn.DDDD -- SVE integer compare with signed immediate
case IF_SVE_CY_3B: // ........xx.iiiii ii.gggnnnnn.DDDD -- SVE integer compare with unsigned immediate
emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), true); // DDDD
emitDispPredicateReg(id->idReg2(), PREDICATE_ZERO, id->idInsOpt(), true); // ggg
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Here we should be using insGetPredicateType(fmt) instead of PREDICATE_ZERO.

But... on the previous line we would still need to do PREDICATE_SIZED.
We could extend insGetPredicateType() to have a an extra arg (reg position), which is ignored for most instructions.

Alternatively, we keep this PR as it is.

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Alternatively, we keep this PR as it is.

I agree. But we should have a follow up PR that calls insGetPredicateType() instead of hard-coding even at other places.

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I agree. But we should have a follow up PR that calls insGetPredicateType() instead of hard-coding even at other places.

Done: #97142

@kunalspathak kunalspathak added the arm-sve Work related to arm64 SVE/SVE2 support label Jan 17, 2024
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LGTM

src/coreclr/jit/emitarm64.cpp
@@ -1072,8 +1072,28 @@ void emitter::emitInsSanityCheck(instrDesc* id)
assert(insOptsScalableWide(id->idInsOpt())); // xx
assert(isPredicateRegister(id->idReg1())); // DDDD
assert(isLowPredicateRegister(id->idReg2())); // ggg
assert(isVectorRegister(id->idReg3())); // mmmmm
assert(isVectorRegister(id->idReg4())); // nnnnn
assert(isVectorRegister(id->idReg3())); // nnnnn
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good catch

src/coreclr/jit/emitarm64.cpp
case IF_SVE_CY_3A: // ........xx.iiiii ...gggnnnnn.DDDD -- SVE integer compare with signed immediate
case IF_SVE_CY_3B: // ........xx.iiiii ii.gggnnnnn.DDDD -- SVE integer compare with unsigned immediate
emitDispPredicateReg(id->idReg1(), PREDICATE_SIZED, id->idInsOpt(), true); // DDDD
emitDispPredicateReg(id->idReg2(), PREDICATE_ZERO, id->idInsOpt(), true); // ggg
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Alternatively, we keep this PR as it is.

I agree. But we should have a follow up PR that calls insGetPredicateType() instead of hard-coding even at other places.

This was referenced Jan 17, 2024
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@kunalspathak kunalspathak merged commit 08cff56 into dotnet:main Jan 17, 2024
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@a74nh a74nh mentioned this pull request Jan 18, 2024
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@SwapnilGaikwad SwapnilGaikwad deleted the github-sve-cy-3a branch January 22, 2024 10:17
tmds pushed a commit to tmds/runtime that referenced this pull request Jan 23, 2024
@SwapnilGaikwad @kunalspathak @tmds
Add Arm64 encodings for IF_SVE_CY_3A and IF_SVE_CY_3B group (dotnet#9…
b96130a 
…6992)

* Add Arm64 encodings for IF_SVE_CY_3A and IF_SVE_CY_3B group

* Fix function declaration

---------

Co-authored-by: Kunal Pathak <Kunal.Pathak@microsoft.com>
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@SwapnilGaikwad @a74nh @kunalspathak