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[RISC-V] Call missing genProduceReg in genCodeForCompare #97805

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merged 1 commit into from
Feb 1, 2024
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[RISC-V] Call missing genProduceReg in genCodeForCompare #97805

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14 changes: 7 additions & 7 deletions src/coreclr/jit/codegenriscv64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3751,9 +3751,13 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree)
emitter* emit = GetEmitter();
regNumber targetReg = tree->GetRegNum();

assert(targetReg != REG_NA);
assert(tree->TypeGet() != TYP_VOID);
assert(!op1->isContainedIntOrIImmed());
assert(tree->OperIs(GT_LT, GT_LE, GT_EQ, GT_NE, GT_GT, GT_GE));

if (varTypeIsFloating(op1Type))
{
assert(tree->OperIs(GT_LT, GT_LE, GT_EQ, GT_NE, GT_GT, GT_GE));
bool isUnordered = (tree->gtFlags & GTF_RELOP_NAN_UN) != 0;
regNumber regOp1 = op1->GetRegNum();
regNumber regOp2 = op2->GetRegNum();
Expand Down Expand Up @@ -3841,12 +3845,6 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree)
}
else
{
assert(targetReg != REG_NA);
assert(tree->TypeGet() != TYP_VOID);

assert(!op1->isContainedIntOrIImmed());
assert(tree->OperIs(GT_LT, GT_LE, GT_EQ, GT_NE, GT_GT, GT_GE));

bool isUnsigned = (tree->gtFlags & GTF_UNSIGNED) != 0;
regNumber regOp1 = op1->GetRegNum();

Expand Down Expand Up @@ -4042,6 +4040,8 @@ void CodeGen::genCodeForCompare(GenTreeOp* tree)
}
}
}

genProduceReg(tree);
}

//------------------------------------------------------------------------
Expand Down
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