Revert "Changes to analog design consistency checks."

[jeffdi]

Reverts #164

[d-m-bailey]

@jeffdi As per my slack comment, you probably want to remerge this.

As you are probably painfully aware, the precheck for analog designs is not passing. I see some changes in caravel/caravel-lite that will solve the current issue, but I think there is another hidden issue. I believe we had a problem before with the requirement that the user_analog_project_wrapper be connected to nets named vccd1_core, vssd1_core etc. At one point this text was added to the layout so the nets would extract with the correct names, but the gds implementation also caused these nets to become ports. Because of the port mismatch, I believe these texts were removed which leaves us with the original problem.
I created a pull request to mpw_precheck that uses caravan.v instead of caravan.spice for the consistency checks. This should work without having to update the caravel/caravel-lite repos.

[RTimothyEdwards]

@d-m-bailey : If we're generating GDS with a recent PDK now, then this issue should be solved---ports should be written to and be read back from GDS correctly.

[d-m-bailey]

@RTimothyEdwards It's not a port issue! It's an internal net issue - is that what you're referring to - being able to label a net without having it extracted as a port?

Incidentally, changing the magic tech file cifin variant may be causing problems in the precheck XOR.

Loading "/Volumes/export/isn/soumil/efabless/mpw_precheck/checks/xor_check/erase_box.tcl" from command line.
"sky130(vendor)" is not one of the CIF input styles Magic knows.