Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Revert "Changes to analog design consistency checks." #166

Merged
merged 1 commit into from
Nov 23, 2022
Merged

Revert "Changes to analog design consistency checks." #166

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 1 addition & 2 deletions checks/consistency_check/consistency_check.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -79,8 +79,7 @@ def main(*args, **kwargs):

# Parse netlists (spice/verilog)
try:
top_netlist_parser = get_netlist_parser(project_config['top_netlist'], project_config['top_module'], 'verilog', include_files=include_files, preprocess_define=PREPROCESS_DEFINES)
#top_netlist_parser = get_netlist_parser(project_config['top_netlist'], project_config['top_module'], project_config['netlist_type'], include_files=include_files, preprocess_define=PREPROCESS_DEFINES)
top_netlist_parser = get_netlist_parser(project_config['top_netlist'], project_config['top_module'], project_config['netlist_type'], include_files=include_files, preprocess_define=PREPROCESS_DEFINES)
user_netlist_parser = get_netlist_parser(project_config['user_netlist'], project_config['user_module'], project_config['netlist_type'], include_files=include_files, preprocess_define=PREPROCESS_DEFINES)
golden_wrapper_parser = VerilogParser(golden_wrapper_netlist, project_config['user_module'], include_files=include_files, preprocess_define=PREPROCESS_DEFINES)
except netlist_parser.DataError as e:
Expand Down
3 changes: 1 addition & 2 deletions checks/utils/utils.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -68,8 +68,7 @@ def get_project_config(project_path, caravel_root):
project_config['top_module'] = 'caravan'
project_config['user_module'] = 'user_analog_project_wrapper'
project_config['golden_wrapper'] = 'user_analog_project_wrapper_empty'
#project_config['top_netlist'] = caravel_root / "spi/lvs/caravan.spice"
project_config['top_netlist'] = caravel_root / "verilog/gl/caravan.v"
project_config['top_netlist'] = caravel_root / "spi/lvs/caravan.spice"
project_config['user_netlist'] = project_path / "netgen/user_analog_project_wrapper.spice"
elif digital_gds_path.exists() and not analog_gds_path.exists():
project_config['type'] = 'digital'
Expand Down