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core/ip: Add optional input buffer on LiteEthIPTX to improve timings.
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enjoy-digital committed Apr 4, 2024
1 parent 30e66a7 commit 211cdc2
Showing 1 changed file with 7 additions and 1 deletion.
8 changes: 7 additions & 1 deletion liteeth/core/ip.py
Original file line number Diff line number Diff line change
Expand Up @@ -94,13 +94,19 @@ def __init__(self, dw=8):


class LiteEthIPTX(LiteXModule):
def __init__(self, mac_address, ip_address, arp_table, dw=8):
def __init__(self, mac_address, ip_address, arp_table, dw=8, with_buffer=False):
self.sink = sink = stream.Endpoint(eth_ipv4_user_description(dw))
self.source = source = stream.Endpoint(eth_mac_description(dw))
self.target_unreachable = Signal()

# # #

# Buffer.
if with_buffer:
self.buffer = buffer = stream.Buffer(eth_ipv4_user_description(dw))
self.comb += sink.connect(buffer.sink)
sink = buffer.source

# Checksum.
self.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True)
self.comb += checksum.ce.eq(sink.valid)
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