bench: Set margin to 0 on 1000/2500BaseX reference clock generation.

enjoy-digital · Jul 10, 2024 · e0f053e · e0f053e
1 parent 08c1077
commit e0f053e
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Showing 4 changed files with 4 additions and 4 deletions.
diff --git a/bench/kc705.py b/bench/kc705.py
@@ -37,7 +37,7 @@ def __init__(self, platform, sys_clk_freq):
         self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
         main_pll.register_clkin(platform.request("clk200"), 200e6)
         main_pll.create_clkout(self.cd_sys, sys_clk_freq)
-        main_pll.create_clkout(self.cd_eth, 200e6)
+        main_pll.create_clkout(self.cd_eth, 200e6, margin=0)
 
 # Bench SoC ----------------------------------------------------------------------------------------
 

diff --git a/bench/kcu105.py b/bench/kcu105.py
@@ -37,7 +37,7 @@ def __init__(self, platform, sys_clk_freq):
         self.comb += main_pll.reset.eq(platform.request("cpu_reset"))
         main_pll.register_clkin(platform.request("clk125"), 125e6)
         main_pll.create_clkout(self.cd_sys, sys_clk_freq)
-        main_pll.create_clkout(self.cd_eth, 200e6)
+        main_pll.create_clkout(self.cd_eth, 200e6, margin=0)
 
 # Bench SoC ----------------------------------------------------------------------------------------
 

diff --git a/bench/xcu1525.py b/bench/xcu1525.py
@@ -37,7 +37,7 @@ def __init__(self, platform, sys_clk_freq):
         self.main_pll = main_pll = USPMMCM(speedgrade=-2)
         main_pll.register_clkin(platform.request("clk300"), 300e6)
         main_pll.create_clkout(self.cd_sys, sys_clk_freq)
-        main_pll.create_clkout(self.cd_eth, 200e6)
+        main_pll.create_clkout(self.cd_eth, 200e6, margin=0)
 
 # Bench SoC ----------------------------------------------------------------------------------------
 

diff --git a/bench/xu8_st1.py b/bench/xu8_st1.py
@@ -36,7 +36,7 @@ def __init__(self, platform, sys_clk_freq):
         self.pll = pll = USMMCM(speedgrade=-1)
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
-        pll.create_clkout(self.cd_eth, 200e6)
+        pll.create_clkout(self.cd_eth, 200e6, margin=0)
 
 # Bench SoC ----------------------------------------------------------------------------------------