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Merge pull request #161 from enjoy-digital/wishbone_tx_rx_buses
mac/wishbone/LiteEthMACWishboneInterface: Expose separate TX/RX Wishb…
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Original file line number | Diff line number | Diff line change |
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@@ -1,67 +1,82 @@ | ||
# | ||
# This file is part of LiteEth. | ||
# | ||
# Copyright (c) 2015-2021 Florent Kermarrec <florent@enjoy-digital.fr> | ||
# Copyright (c) 2015-2024 Florent Kermarrec <florent@enjoy-digital.fr> | ||
# Copyright (c) 2015-2016 Sebastien Bourdeauducq <sb@m-labs.hk> | ||
# Copyright (c) 2021 Leon Schuermann <leon@is.currently.online> | ||
# SPDX-License-Identifier: BSD-2-Clause | ||
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import math | ||
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from litex.gen import * | ||
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from liteeth.common import * | ||
from liteeth.mac import sram | ||
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from litex.soc.interconnect import wishbone | ||
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# MAC Wishbone Interface --------------------------------------------------------------------------- | ||
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class LiteEthMACWishboneInterface(Module, AutoCSR): | ||
class LiteEthMACWishboneInterface(LiteXModule): | ||
def __init__(self, dw, nrxslots=2, ntxslots=2, endianness="big", timestamp=None, | ||
rxslots_read_only = True, | ||
txslots_write_only = False, | ||
): | ||
self.sink = stream.Endpoint(eth_phy_description(dw)) | ||
self.source = stream.Endpoint(eth_phy_description(dw)) | ||
self.bus = wishbone.Interface(data_width=dw) | ||
self.bus_rx = wishbone.Interface(data_width=dw) | ||
self.bus_tx = wishbone.Interface(data_width=dw) | ||
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# # # | ||
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# Storage in SRAM. | ||
# ---------------- | ||
sram_depth = math.ceil(eth_mtu/(dw//8)) | ||
self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness, timestamp) | ||
self.comb += self.sink.connect(self.sram.sink) | ||
self.comb += self.sram.source.connect(self.source) | ||
self.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots, endianness, timestamp) | ||
self.comb += [ | ||
self.sink.connect(self.sram.sink), | ||
self.sram.source.connect(self.source), | ||
] | ||
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# Wishbone SRAM interfaces for the writer SRAM (i.e. Ethernet RX). | ||
wb_rx_sram_ifs = [] | ||
for n in range(nrxslots): | ||
wb_rx_sram_ifs.append(wishbone.SRAM( | ||
mem_or_size = self.sram.writer.mems[n], | ||
read_only = rxslots_read_only, | ||
bus = wishbone.Interface(data_width = dw) | ||
)) | ||
# Ethernet Wishbone SRAM interfaces exposure. | ||
# ------------------------------------------- | ||
self._expose_wishbone_sram_interfaces( | ||
bus = self.bus_rx, | ||
dw = dw, | ||
mems = self.sram.writer.mems, | ||
nslots = nrxslots, | ||
read_only = rxslots_read_only, | ||
write_only = False, | ||
) | ||
self._expose_wishbone_sram_interfaces( | ||
bus = self.bus_tx, | ||
dw = dw, | ||
mems = self.sram.reader.mems, | ||
nslots = ntxslots, | ||
read_only = False, | ||
write_only = txslots_write_only, | ||
) | ||
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# Wishbone SRAM interfaces for the reader SRAM (i.e. Ethernet TX). | ||
wb_tx_sram_ifs = [] | ||
for n in range(ntxslots): | ||
wb_tx_sram_ifs.append(wishbone.SRAM( | ||
mem_or_size = self.sram.reader.mems[n], | ||
write_only = txslots_write_only, | ||
bus = wishbone.Interface(data_width = dw) | ||
def _expose_wishbone_sram_interfaces(self, bus, dw, mems, nslots, read_only, write_only): | ||
# SRAMs. | ||
wb_sram_ifs = [] | ||
for n in range(nslots): | ||
wb_sram_ifs.append(wishbone.SRAM( | ||
mem_or_size = mems[n], | ||
read_only = read_only, | ||
write_only = write_only, | ||
bus = wishbone.Interface(data_width=dw) | ||
)) | ||
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# Expose Wishbone SRAMs on a single Wishbone bus. | ||
# CHECKME: Check Decoder width for 64-bit. | ||
# Expose SRAMs on Bus. | ||
wb_slaves = [] | ||
sram_depth = math.ceil(eth_mtu/(dw//8)) | ||
decoderoffset = log2_int(sram_depth, need_pow2=False) | ||
rx_decoderbits = log2_int(len(wb_rx_sram_ifs)) | ||
tx_decoderbits = log2_int(len(wb_tx_sram_ifs)) | ||
decoderbits = max(rx_decoderbits, tx_decoderbits) + 1 | ||
wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs | ||
decoderbits = log2_int(len(wb_sram_ifs)) | ||
for n, wb_sram_if in enumerate(wb_sram_ifs): | ||
def slave_filter(a, v=n): | ||
return a[decoderoffset:decoderoffset+decoderbits] == v | ||
wb_slaves.append((slave_filter, wb_sram_if.bus)) | ||
self.submodules += wb_sram_if | ||
wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True) | ||
wb_con = wishbone.Decoder(bus, wb_slaves, register=True) | ||
self.submodules += wb_con |
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