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phy/1000basex: Move Gearbox to pcs_1000basex since common and rename …
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…it to PCSGearbox.
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enjoy-digital committed Jun 13, 2023
1 parent be9f26e commit ee9d9e3
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Showing 5 changed files with 33 additions and 121 deletions.
32 changes: 1 addition & 31 deletions liteeth/phy/a7_1000basex.py
Original file line number Diff line number Diff line change
Expand Up @@ -17,34 +17,6 @@
from liteeth.phy.a7_gtp import *
from liteeth.phy.pcs_1000basex import *

# Gearbox ------------------------------------------------------------------------------------------

class Gearbox(LiteXModule):
def __init__(self):
self.tx_data = Signal(10)
self.tx_data_half = Signal(20)
self.rx_data_half = Signal(20)
self.rx_data = Signal(10)

# TX
buf = Signal(20)
self.sync.eth_tx += buf.eq(Cat(buf[10:], self.tx_data))
self.sync.eth_tx_half += self.tx_data_half.eq(buf)

# RX
phase_half = Signal()
phase_half_rereg = Signal()
self.sync.eth_rx_half += phase_half_rereg.eq(phase_half)
self.sync.eth_rx += [
If(phase_half == phase_half_rereg,
self.rx_data.eq(self.rx_data_half[10:])
).Else(
self.rx_data.eq(self.rx_data_half[:10])
),
phase_half.eq(~phase_half),
]


# A7_1000BASEX PHY ---------------------------------------------------------------------------------

class A7_1000BASEX(LiteXModule):
Expand Down Expand Up @@ -792,9 +764,7 @@ def __init__(self, qpll_channel, data_pads, sys_clk_freq, with_csr=True, rx_pola
rx_mmcm_reset.attr.add("no_retiming")

# Gearbox and PCS connection
gearbox = Gearbox()
self.submodules += gearbox

self.gearbox = gearbox = PCSGearbox()
self.comb += [
tx_data.eq(gearbox.tx_data_half),
gearbox.rx_data_half.eq(rx_data),
Expand Down
31 changes: 1 addition & 30 deletions liteeth/phy/k7_1000basex.py
Original file line number Diff line number Diff line change
Expand Up @@ -17,33 +17,6 @@
from liteeth.common import *
from liteeth.phy.pcs_1000basex import *

# Gearbox ------------------------------------------------------------------------------------------

class Gearbox(LiteXModule):
def __init__(self):
self.tx_data = Signal(10)
self.tx_data_half = Signal(20)
self.rx_data_half = Signal(20)
self.rx_data = Signal(10)

# TX
buf = Signal(20)
self.sync.eth_tx += buf.eq(Cat(buf[10:], self.tx_data))
self.sync.eth_tx_half += self.tx_data_half.eq(buf)

# RX
phase_half = Signal()
phase_half_rereg = Signal()
self.sync.eth_rx_half += phase_half_rereg.eq(phase_half)
self.sync.eth_rx += [
If(phase_half == phase_half_rereg,
self.rx_data.eq(self.rx_data_half[10:])
).Else(
self.rx_data.eq(self.rx_data_half[:10])
),
phase_half.eq(~phase_half),
]

# K7_1000BASEX PHY ---------------------------------------------------------------------------------

class K7_1000BASEX(LiteXModule):
Expand Down Expand Up @@ -811,9 +784,7 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq, with_csr=True, r
rx_mmcm_reset.attr.add("no_retiming")

# Gearbox and PCS connection
gearbox = Gearbox()
self.submodules += gearbox

self.gearbox = gearbox = PCSGearbox()
self.comb += [
tx_data.eq(gearbox.tx_data_half),
gearbox.rx_data_half.eq(rx_data),
Expand Down
31 changes: 1 addition & 30 deletions liteeth/phy/ku_1000basex.py
Original file line number Diff line number Diff line change
Expand Up @@ -14,33 +14,6 @@
from liteeth.common import *
from liteeth.phy.pcs_1000basex import *

# Gearbox ------------------------------------------------------------------------------------------

class Gearbox(LiteXModule):
def __init__(self):
self.tx_data = Signal(10)
self.tx_data_half = Signal(20)
self.rx_data_half = Signal(20)
self.rx_data = Signal(10)

# TX
buf = Signal(20)
self.sync.eth_tx += buf.eq(Cat(buf[10:], self.tx_data))
self.sync.eth_tx_half += self.tx_data_half.eq(buf)

# RX
phase_half = Signal()
phase_half_rereg = Signal()
self.sync.eth_rx_half += phase_half_rereg.eq(phase_half)
self.sync.eth_rx += [
If(phase_half == phase_half_rereg,
self.rx_data.eq(self.rx_data_half[10:])
).Else(
self.rx_data.eq(self.rx_data_half[:10])
),
phase_half.eq(~phase_half),
]

# KU_1000BASEX PHY ---------------------------------------------------------------------------------

class KU_1000BASEX(LiteXModule):
Expand Down Expand Up @@ -867,9 +840,7 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq):
]

# Gearbox and PCS connection
gearbox = Gearbox()
self.submodules += gearbox

self.gearbox = gearbox = PCSGearbox()
self.comb += [
tx_data.eq(gearbox.tx_data_half),
gearbox.rx_data_half.eq(rx_data),
Expand Down
29 changes: 29 additions & 0 deletions liteeth/phy/pcs_1000basex.py
Original file line number Diff line number Diff line change
Expand Up @@ -257,6 +257,35 @@ def __init__(self, lsb_first=False):
)
)

# PCS Gearbox --------------------------------------------------------------------------------------

class PCSGearbox(LiteXModule):
def __init__(self):
self.tx_data = Signal(10)
self.tx_data_half = Signal(20)
self.rx_data_half = Signal(20)
self.rx_data = Signal(10)

# # #

# TX
buf = Signal(20)
self.sync.eth_tx += buf.eq(Cat(buf[10:], self.tx_data))
self.sync.eth_tx_half += self.tx_data_half.eq(buf)

# RX
phase_half = Signal()
phase_half_rereg = Signal()
self.sync.eth_rx_half += phase_half_rereg.eq(phase_half)
self.sync.eth_rx += [
If(phase_half == phase_half_rereg,
self.rx_data.eq(self.rx_data_half[10:])
).Else(
self.rx_data.eq(self.rx_data_half[:10])
),
phase_half.eq(~phase_half),
]

# PCS ----------------------------------------------------------------------------------------------

class PCS(LiteXModule):
Expand Down
31 changes: 1 addition & 30 deletions liteeth/phy/usp_1000basex.py
Original file line number Diff line number Diff line change
Expand Up @@ -16,33 +16,6 @@
from liteeth.common import *
from liteeth.phy.pcs_1000basex import *

# Gearbox ------------------------------------------------------------------------------------------

class Gearbox(LiteXModule):
def __init__(self):
self.tx_data = Signal(10)
self.tx_data_half = Signal(20)
self.rx_data_half = Signal(20)
self.rx_data = Signal(10)

# TX
buf = Signal(20)
self.sync.eth_tx += buf.eq(Cat(buf[10:], self.tx_data))
self.sync.eth_tx_half += self.tx_data_half.eq(buf)

# RX
phase_half = Signal()
phase_half_rereg = Signal()
self.sync.eth_rx_half += phase_half_rereg.eq(phase_half)
self.sync.eth_rx += [
If(phase_half == phase_half_rereg,
self.rx_data.eq(self.rx_data_half[10:])
).Else(
self.rx_data.eq(self.rx_data_half[:10])
),
phase_half.eq(~phase_half),
]

# USP_1000BASEX PHY ---------------------------------------------------------------------------------

class USP_1000BASEX(LiteXModule):
Expand Down Expand Up @@ -977,9 +950,7 @@ def __init__(self, refclk_or_clk_pads, data_pads, sys_clk_freq):
]

# Gearbox and PCS connection
gearbox = Gearbox()
self.submodules += gearbox

self.gearbox = gearbox = PCSGearbox()
self.comb += [
tx_data.eq(gearbox.tx_data_half),
gearbox.rx_data_half.eq(rx_data),
Expand Down

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