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bench/serdes: Minor cleanup and updates.
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@enjoy-digital
enjoy-digital committed Feb 28, 2024
1 parent 39824a4 commit c045149
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Showing 7 changed files with 169 additions and 119 deletions.
70 changes: 45 additions & 25 deletions bench/serdes/ecpix5.py
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Original file line number Diff line number Diff line change
Expand Up @@ -3,10 +3,11 @@
#
# This file is part of LiteICLink.
#
# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2019-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause

import sys
import time
import argparse

from migen import *
Expand All @@ -25,13 +26,15 @@

from liteiclink.serdes.serdes_ecp5 import SerDesECP5PLL, SerDesECP5

from litescope import LiteScopeAnalyzer

# IOs ----------------------------------------------------------------------------------------------

_transceiver_io = [
# SATA
# SATA.
("sata_clk", 0,
Subsignal("p", Pins("AF12")),
Subsignal("n", Pins("AF13"))
Subsignal("n", Pins("AF13")),
),
("sata_tx", 0,
Subsignal("p", Pins("AD16")),
Expand All @@ -53,19 +56,22 @@ def __init__(self, platform, sys_clk_freq, refclk_from_pll, refclk_freq):

# # #

# Clk / Rst
# Clk / Rst.
# ----------
clk100 = platform.request("clk100")
rst_n = platform.request("rst_n")
platform.add_period_constraint(clk100, 1e9/100e6)

# Power on reset
# Power on reset.
# ---------------
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))

# PLL
# PLL.
# ----
self.pll = pll = ECP5PLL()
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
Expand All @@ -87,18 +93,19 @@ def __init__(self, platform, linerate=2.5e9):

# CRG --------------------------------------------------------------------------------------
refclk_from_pll = {
1.25e9: False, # SGMII
1.5e9: True, # SATA Gen1
2.5e9: False, # PCIe Gen1
3.0e9: True, # SATA Gen2
1.25e9: False, # SGMII.
1.5e9: True, # SATA Gen1.
2.5e9: False, # PCIe Gen1.
3.0e9: True, # SATA Gen2.
5.0e9: True, # PCIe Gen2, USB3.
}[linerate]
refclk_freq = {
1.25e9: 100e6,
1.5e9: 150e6,
2.5e9: 100e6,
3.0e9: 150e6,
5.0e9: 250e6}[linerate]
5.0e9: 250e6,
}[linerate]
self.crg = _CRG(platform, sys_clk_freq, refclk_from_pll, refclk_freq)

# SerDes RefClk ----------------------------------------------------------------------------
Expand All @@ -112,20 +119,29 @@ def __init__(self, platform, linerate=2.5e9):
i_REFCLKN = refclk_pads.n,
o_REFCLKO = refclk,
p_REFCK_PWDNB = "0b1",
p_REFCK_RTERM = "0b0", # terminated externally
p_REFCK_RTERM = "0b0", # Terminated externally.
)
self.extref0.attr.add(("LOC", "EXTREF1"))

# SerDes PLL -------------------------------------------------------------------------------
serdes_pll = SerDesECP5PLL(refclk, refclk_freq=refclk_freq, linerate=linerate)
self.submodules += serdes_pll
self.serdes_pll = serdes_pll = SerDesECP5PLL(
refclk = refclk,
refclk_freq = refclk_freq,
linerate = linerate,
)
print(serdes_pll)

# SerDes -----------------------------------------------------------------------------------
tx_pads = platform.request("sata_tx")
rx_pads = platform.request("sata_rx")
self.serdes0 = serdes0 = SerDesECP5(serdes_pll, tx_pads, rx_pads,
dual=1, channel=0, data_width=20)
self.serdes0 = serdes0 = SerDesECP5(
pll = serdes_pll,
tx_pads = tx_pads,
rx_pads = rx_pads,
dual = 1,
channel = 0,
data_width = 20,
)
serdes0.add_stream_endpoints()
serdes0.add_controls()
serdes0.add_clock_cycles()
Expand All @@ -137,15 +153,17 @@ def __init__(self, platform, linerate=2.5e9):
counter = Signal(32)
self.sync.tx += counter.eq(counter + 1)

# K28.5 and slow counter --> TX
# K28.5 and slow counter --> TX.
# ------------------------------
self.comb += [
serdes0.sink.valid.eq(1),
serdes0.sink.ctrl.eq(0b1),
serdes0.sink.data[:8].eq(K(28, 5)),
serdes0.sink.data[8:].eq(counter[26:]),
]

# RX (slow counter) --> Leds
# RX (slow counter) --> Leds.
# ---------------------------
counter = Signal(8)
self.sync.rx += [
serdes0.rx_align.eq(1),
Expand All @@ -172,14 +190,17 @@ def __init__(self, platform, linerate=2.5e9):
self.sync.tx += tx_counter.eq(tx_counter + 1)
self.comb += platform.request("rgb_led", 2).g.eq(tx_counter[26])

# # Analyzer ---------------------------------------------------------------------------------
from litescope import LiteScopeAnalyzer
self.analyzer = LiteScopeAnalyzer([
# Analyzer ---------------------------------------------------------------------------------
analyzer_signals = [
serdes0.init.fsm,
serdes0.init.tx_lol,
serdes0.init.rx_lol,
], depth=512)

]
self.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = "sys",
csr_csv = "analyzer.csv",
)

# Build --------------------------------------------------------------------------------------------

Expand All @@ -195,9 +216,8 @@ def main():
platform = lambdaconcept_ecpix5.Platform(device=args.device, toolchain=args.toolchain)
platform.add_extension(_transceiver_io)
soc = SerDesTestSoC(platform,
linerate = float(args.linerate)
linerate = float(args.linerate),
)
import time
time.sleep(1) # Yosys/NextPnr are too fast, add sleep to see LiteX logs :)
builder = Builder(soc, csr_csv="csr.csv")
builder.build(run=args.build)
Expand Down
31 changes: 17 additions & 14 deletions bench/serdes/kc705.py
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
#
# This file is part of LiteICLink.
#
# Copyright (c) 2017-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2017-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause

import sys
Expand All @@ -27,24 +27,24 @@
# IOs ----------------------------------------------------------------------------------------------

_transceiver_io = [
# PCIe
# PCIe.
("pcie_tx", 0,
Subsignal("p", Pins("L4")),
Subsignal("n", Pins("L3"))
Subsignal("n", Pins("L3")),
),
("pcie_rx", 0,
Subsignal("p", Pins("M6")),
Subsignal("n", Pins("M5"))
Subsignal("n", Pins("M5")),
),
# SFP: Already provided by KC705 platform.
# SMA
# SMA.
("sma_tx", 0,
Subsignal("p", Pins("K2")),
Subsignal("n", Pins("K1"))
Subsignal("n", Pins("K1")),
),
("sma_rx", 0,
Subsignal("p", Pins("K6")),
Subsignal("n", Pins("K5"))
Subsignal("n", Pins("K5")),
),
]

Expand Down Expand Up @@ -72,21 +72,22 @@ def __init__(self, platform, connector="pcie", linerate=2.5e9, use_qpll=False):
i_CEB = 0,
i_I = refclk_pads.p,
i_IB = refclk_pads.n,
o_O = refclk)
o_O = refclk,
)

# GTX PLL ----------------------------------------------------------------------------------
pll_cls = GTXQuadPLL if use_qpll else GTXChannelPLL
pll = pll_cls(refclk, 125e6, linerate)
self.pll = pll = pll_cls(refclk, 125e6, linerate)
print(pll)
self.submodules += pll

# GTX --------------------------------------------------------------------------------------
tx_pads = platform.request(connector + "_tx")
rx_pads = platform.request(connector + "_rx")
self.serdes0 = serdes0 = GTX(pll, tx_pads, rx_pads, sys_clk_freq,
tx_buffer_enable = True,
rx_buffer_enable = True,
clock_aligner = False)
clock_aligner = False,
)
serdes0.add_stream_endpoints()
serdes0.add_controls()
serdes0.add_clock_cycles()
Expand All @@ -102,15 +103,17 @@ def __init__(self, platform, connector="pcie", linerate=2.5e9, use_qpll=False):
counter = Signal(32)
self.sync.tx += counter.eq(counter + 1)

# K28.5 and slow counter --> TX
# K28.5 and slow counter --> TX.
# ------------------------------
self.comb += [
serdes0.sink.valid.eq(1),
serdes0.sink.ctrl.eq(0b1),
serdes0.sink.data[:8].eq(K(28, 5)),
serdes0.sink.data[8:].eq(counter[26:]),
]

# RX (slow counter) --> Leds
# RX (slow counter) --> Leds.
# ---------------------------
for i in range(4):
self.comb += platform.request("user_led", 4 + i).eq(serdes0.source.data[i])

Expand Down Expand Up @@ -143,7 +146,7 @@ def main():
soc = GTXTestSoC(platform,
connector = args.connector,
linerate = float(args.linerate),
use_qpll = args.pll == "qpll"
use_qpll = args.pll == "qpll",
)
builder = Builder(soc, csr_csv="kc705.csv")
builder.build(run=args.build)
Expand Down

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