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PAC update #2378

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merged 2 commits into from
Oct 22, 2024
Merged

PAC update #2378

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53c4a87
PAC update
bugadani Oct 16, 2024
1ae68be
Inline steals into reg expressions
bugadani Oct 21, 2024
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14 changes: 7 additions & 7 deletions esp-hal/Cargo.toml
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Original file line number Diff line number Diff line change
Expand Up @@ -55,13 +55,13 @@ xtensa-lx = { version = "0.9.0", optional = true }
# IMPORTANT:
# Each supported device MUST have its PAC included below along with a
# corresponding feature.
esp32 = { version = "0.33.0", features = ["critical-section", "rt"], optional = true }
esp32c2 = { version = "0.22.0", features = ["critical-section", "rt"], optional = true }
esp32c3 = { version = "0.25.0", features = ["critical-section", "rt"], optional = true }
esp32c6 = { version = "0.16.0", features = ["critical-section", "rt"], optional = true }
esp32h2 = { version = "0.12.0", features = ["critical-section", "rt"], optional = true }
esp32s2 = { version = "0.24.0", features = ["critical-section", "rt"], optional = true }
esp32s3 = { version = "0.28.0", features = ["critical-section", "rt"], optional = true }
esp32 = { version = "0.33.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "317f89c", features = ["critical-section", "rt"], optional = true }
esp32c2 = { version = "0.22.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "317f89c", features = ["critical-section", "rt"], optional = true }
esp32c3 = { version = "0.25.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "317f89c", features = ["critical-section", "rt"], optional = true }
esp32c6 = { version = "0.16.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "317f89c", features = ["critical-section", "rt"], optional = true }
esp32h2 = { version = "0.12.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "317f89c", features = ["critical-section", "rt"], optional = true }
esp32s2 = { version = "0.24.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "317f89c", features = ["critical-section", "rt"], optional = true }
esp32s3 = { version = "0.28.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "317f89c", features = ["critical-section", "rt"], optional = true }

[target.'cfg(target_arch = "riscv32")'.dependencies]
esp-riscv-rt = { version = "0.9.0", path = "../esp-riscv-rt" }
Expand Down
199 changes: 100 additions & 99 deletions esp-hal/src/gpio/lp_io.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -28,18 +28,24 @@

use core::marker::PhantomData;

use super::{InputPin, OutputPin, RtcPin};
use crate::{
peripheral::Peripheral,
peripherals::{GPIO, LP_AON, LP_IO},
};

/// A GPIO output pin configured for low power operation
pub struct LowPowerOutput<'d, const PIN: u8> {
phantom: PhantomData<&'d ()>,
}

impl<'d, const PIN: u8> LowPowerOutput<'d, PIN> {
/// Create a new output pin for use by the low-power core
pub fn new<P>(_pin: impl crate::peripheral::Peripheral<P = P> + 'd) -> Self
pub fn new<P>(_pin: impl Peripheral<P = P> + 'd) -> Self
where
P: super::OutputPin + RtcPin,
P: OutputPin + RtcPin,
{
crate::gpio::lp_io::init_low_power_pin(PIN);
init_low_power_pin(PIN);

let this = Self {
phantom: PhantomData,
Expand All @@ -50,7 +56,7 @@ impl<'d, const PIN: u8> LowPowerOutput<'d, PIN> {
}

fn output_enable(&self, enable: bool) {
let lp_io = unsafe { &*crate::peripherals::LP_IO::PTR };
let lp_io = unsafe { LP_IO::steal() };
if enable {
lp_io
.out_enable_w1ts()
Expand All @@ -70,11 +76,11 @@ pub struct LowPowerInput<'d, const PIN: u8> {

impl<'d, const PIN: u8> LowPowerInput<'d, PIN> {
/// Create a new input pin for use by the low-power core
pub fn new<P>(_pin: impl crate::peripheral::Peripheral<P = P> + 'd) -> Self
pub fn new<P>(_pin: impl Peripheral<P = P> + 'd) -> Self
where
P: super::InputPin + RtcPin,
P: InputPin + RtcPin,
{
crate::gpio::lp_io::init_low_power_pin(PIN);
init_low_power_pin(PIN);

let this = Self {
phantom: PhantomData,
Expand All @@ -87,17 +93,23 @@ impl<'d, const PIN: u8> LowPowerInput<'d, PIN> {
}

fn input_enable(&self, enable: bool) {
get_pin_reg(PIN).modify(|_, w| w.fun_ie().bit(enable));
unsafe { LP_IO::steal() }
.gpio(PIN as usize)
.modify(|_, w| w.fun_ie().bit(enable));
}

/// Sets pull-up enable for the pin
pub fn pullup_enable(&self, enable: bool) {
get_pin_reg(PIN).modify(|_, w| w.fun_wpu().bit(enable));
unsafe { LP_IO::steal() }
.gpio(PIN as usize)
.modify(|_, w| w.fun_wpu().bit(enable));
}

/// Sets pull-down enable for the pin
pub fn pulldown_enable(&self, enable: bool) {
get_pin_reg(PIN).modify(|_, w| w.fun_wpd().bit(enable));
unsafe { LP_IO::steal() }
.gpio(PIN as usize)
.modify(|_, w| w.fun_wpd().bit(enable));
}
}

Expand All @@ -108,11 +120,11 @@ pub struct LowPowerOutputOpenDrain<'d, const PIN: u8> {

impl<'d, const PIN: u8> LowPowerOutputOpenDrain<'d, PIN> {
/// Create a new output pin for use by the low-power core
pub fn new<P>(_pin: impl crate::peripheral::Peripheral<P = P> + 'd) -> Self
pub fn new<P>(_pin: impl Peripheral<P = P> + 'd) -> Self
where
P: super::InputPin + super::OutputPin + RtcPin,
P: InputPin + OutputPin + RtcPin,
{
crate::gpio::lp_io::init_low_power_pin(PIN);
init_low_power_pin(PIN);

let this = Self {
phantom: PhantomData,
Expand All @@ -128,7 +140,7 @@ impl<'d, const PIN: u8> LowPowerOutputOpenDrain<'d, PIN> {
}

fn output_enable(&self, enable: bool) {
let lp_io = unsafe { &*crate::peripherals::LP_IO::PTR };
let lp_io = unsafe { LP_IO::steal() };
if enable {
lp_io
.out_enable_w1ts()
Expand All @@ -141,48 +153,40 @@ impl<'d, const PIN: u8> LowPowerOutputOpenDrain<'d, PIN> {
}

fn input_enable(&self, enable: bool) {
get_pin_reg(PIN).modify(|_, w| w.fun_ie().bit(enable));
unsafe { LP_IO::steal() }
.gpio(PIN as usize)
.modify(|_, w| w.fun_ie().bit(enable));
}

/// Sets pull-up enable for the pin
pub fn pullup_enable(&self, enable: bool) {
get_pin_reg(PIN).modify(|_, w| w.fun_wpu().bit(enable));
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Might've been worth keeping the get_pin_reg function still. 😅

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It's impossible if we use ::steal() because it would return a reference to a local now. We don't have to use steal, thoguh, but it looks better to my brain than random pointer dereferencing.

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but it looks better to my brain than random pointer dereferencing

Same 😄

unsafe { LP_IO::steal() }
.gpio(PIN as usize)
.modify(|_, w| w.fun_wpu().bit(enable));
}

/// Sets pull-down enable for the pin
pub fn pulldown_enable(&self, enable: bool) {
get_pin_reg(PIN).modify(|_, w| w.fun_wpd().bit(enable));
unsafe { LP_IO::steal() }
.gpio(PIN as usize)
.modify(|_, w| w.fun_wpd().bit(enable));
}

fn set_open_drain_output(&self, enable: bool) {
use crate::peripherals::GPIO;
let gpio = unsafe { &*GPIO::PTR };

gpio.pin(PIN as usize)
unsafe { GPIO::steal() }
.pin(PIN as usize)
.modify(|_, w| w.pad_driver().bit(enable));
}
}

pub(crate) fn init_low_power_pin(pin: u8) {
let lp_aon = unsafe { &*crate::peripherals::LP_AON::PTR };

lp_aon
unsafe { LP_AON::steal() }
.gpio_mux()
.modify(|r, w| unsafe { w.sel().bits(r.sel().bits() | 1 << pin) });

get_pin_reg(pin).modify(|_, w| unsafe { w.mcu_sel().bits(0) });
}

#[inline(always)]
fn get_pin_reg(pin: u8) -> &'static crate::peripherals::lp_io::GPIO0 {
// ideally we should change the SVD and make the GPIOx registers into an
// array
unsafe {
let lp_io = &*crate::peripherals::LP_IO::PTR;
let pin_ptr = (lp_io.gpio0().as_ptr()).add(pin as usize);

&*(pin_ptr as *const crate::peripherals::lp_io::GPIO0)
}
unsafe { LP_IO::steal() }
.gpio(pin as usize)
.modify(|_, w| unsafe { w.mcu_sel().bits(0) });
}

#[doc(hidden)]
Expand All @@ -191,77 +195,76 @@ macro_rules! lp_gpio {
(
$($gpionum:literal)+
) => {
paste::paste!{
$(
impl $crate::gpio::RtcPin for GpioPin<$gpionum> {
unsafe fn apply_wakeup(&mut self, wakeup: bool, level: u8) {
let lp_io = &*$crate::peripherals::LP_IO::ptr();
lp_io.[< pin $gpionum >]().modify(|_, w| {
w.wakeup_enable().bit(wakeup).int_type().bits(level)
$(
impl $crate::gpio::RtcPin for GpioPin<$gpionum> {
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With the new PAC update, this impl can be moved out of the macro. I'm hoping to see this in some future PR.

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@bugadani bugadani Oct 21, 2024 •
edited
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That was one of the main motivators behind the relevant PAC change, and we're almost there.

unsafe fn apply_wakeup(&mut self, wakeup: bool, level: u8) {
let lp_io = $crate::peripherals::LP_IO::steal();
lp_io.pin($gpionum).modify(|_, w| {
w.wakeup_enable().bit(wakeup).int_type().bits(level)
});
}

fn rtcio_pad_hold(&mut self, enable: bool) {
let mask = 1 << $gpionum;
unsafe {
let lp_aon = $crate::peripherals::LP_AON::steal();

lp_aon.gpio_hold0().modify(|r, w| {
if enable {
w.gpio_hold0().bits(r.gpio_hold0().bits() | mask)
} else {
w.gpio_hold0().bits(r.gpio_hold0().bits() & !mask)
}
});
}
}

fn rtcio_pad_hold(&mut self, enable: bool) {
let mask = 1 << $gpionum;
unsafe {
let lp_aon = &*$crate::peripherals::LP_AON::ptr();

lp_aon.gpio_hold0().modify(|r, w| {
if enable {
w.gpio_hold0().bits(r.gpio_hold0().bits() | mask)
/// Set the LP properties of the pin. If `mux` is true then then pin is
/// routed to LP_IO, when false it is routed to IO_MUX.
fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: $crate::gpio::RtcFunction) {
let mask = 1 << $gpionum;
unsafe {
// Select LP_IO
let lp_aon = $crate::peripherals::LP_AON::steal();
lp_aon
.gpio_mux()
.modify(|r, w| {
if mux {
w.sel().bits(r.sel().bits() | mask)
} else {
w.gpio_hold0().bits(r.gpio_hold0().bits() & !mask)
w.sel().bits(r.sel().bits() & !mask)
}
});
}
}

/// Set the LP properties of the pin. If `mux` is true then then pin is
/// routed to LP_IO, when false it is routed to IO_MUX.
fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: $crate::gpio::RtcFunction) {
let mask = 1 << $gpionum;
unsafe {
// Select LP_IO
let lp_aon = &*$crate::peripherals::LP_AON::ptr();
lp_aon
.gpio_mux()
.modify(|r, w| {
if mux {
w.sel().bits(r.sel().bits() | mask)
} else {
w.sel().bits(r.sel().bits() & !mask)
}
});

// Configure input, function and select normal operation registers
let lp_io = &*$crate::peripherals::LP_IO::ptr();
lp_io.[< gpio $gpionum >]().modify(|_, w| {
w
.slp_sel().bit(false)
.fun_ie().bit(input_enable)
.mcu_sel().bits(func as u8)
});
}
// Configure input, function and select normal operation registers
let lp_io = $crate::peripherals::LP_IO::steal();
lp_io.gpio($gpionum).modify(|_, w| {
w.slp_sel().bit(false);
w.fun_ie().bit(input_enable);
w.mcu_sel().bits(func as u8)
});
}
}
}

impl $crate::gpio::RtcPinWithResistors for GpioPin<$gpionum> {
fn rtcio_pullup(&mut self, enable: bool) {
let lp_io = unsafe { &*$crate::peripherals::LP_IO::ptr() };
lp_io.[< gpio $gpionum >]().modify(|_, w| w.fun_wpu().bit(enable));
}
impl $crate::gpio::RtcPinWithResistors for GpioPin<$gpionum> {
fn rtcio_pullup(&mut self, enable: bool) {
let lp_io = unsafe { $crate::peripherals::LP_IO::steal() };
lp_io.gpio($gpionum).modify(|_, w| w.fun_wpu().bit(enable));
}

fn rtcio_pulldown(&mut self, enable: bool) {
let lp_io = unsafe { &*$crate::peripherals::LP_IO::ptr() };
lp_io.[< gpio $gpionum >]().modify(|_, w| w.fun_wpd().bit(enable));
}
fn rtcio_pulldown(&mut self, enable: bool) {
let lp_io = unsafe { $crate::peripherals::LP_IO::steal() };
lp_io.gpio($gpionum).modify(|_, w| w.fun_wpd().bit(enable));
}
)+
}
)+

#[doc(hidden)]
#[macro_export]
macro_rules! handle_rtcio {
($this:expr, $inner:ident, $code:tt) => {
#[doc(hidden)]
#[macro_export]
macro_rules! handle_rtcio {
($this:expr, $inner:ident, $code:tt) => {
paste::paste! {
match $this {
$(
AnyPinInner::[<Gpio $gpionum >]($inner) => {
Expand All @@ -273,12 +276,10 @@ macro_rules! lp_gpio {
}
}
}
pub(crate) use handle_rtcio;
pub(crate) use handle_rtcio as handle_rtcio_with_resistors;
}
pub(crate) use handle_rtcio;
pub(crate) use handle_rtcio as handle_rtcio_with_resistors;
}
}

pub(crate) use lp_gpio;

use super::RtcPin;
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