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@gerekon gerekon released this 10 Apr 14:15
· 1 commit to xtensa_release_17.0.1 since this release
esp-17.0.1_20240408
b02b417

Changes (since esp-16.0.4-20231113):

Features:

  • Upgraded LLVM ver to 17.0.1.
  • [Toolchain][Espressif]: Upgraded binutils version to 'esp-2.41.0_20240305'.
  • [Toolchain][Espressif]: Upgraded newlib version to 'esp-4.3.0_20240322'.
  • [Toolchain][Espressif]: Upgraded libstdc++ and libgcc to '13.2.0_20240305'.
  • [Toolchain][RISCV][Xtensa] Added Espressif baremetal toolchain.
  • [Toolchain][RISCV][Xtensa] Removed GCC installation support for Espressif toolchain. Now picking up multilibs from existing GCC installation is not possible.
  • [RISCV] Add 'tcontrol' CSR register.
  • [Xtensa] Add predefined macros for core configuration. Now every configrable option for Xtensa core can be checked using pre-defined macro as it is done in GCC 13.
  • [Xtensa] Implement support for __attribute__((short__call)) and __attribute__((near)). Related to #90.
  • [Xtensa] Add vector conversion builtins. Closes #89.
  • [Xtensa] Add support for boolean vectors. Closes #89.
  • [Xtensa] Add HIFI3 C types and intrinsics. Closes #89.
  • [Xtensa] Add HIFI3 target feature. Closes #89.
  • [Xtensa] Make assembler output compatible with GAS. Some Xtensa targets may still use GAS as a default assembler through '-fno-integrated-as option'. These changes make the assembly output compatible with GAS by default.
  • [Xtensa] Add Cannonlake CPU. Added a definition of Xtensa LX6 CPU variant present in Intel Cannonlake and Tigerlake SOC platforms. Closes #89.
  • [Xtensa] Add float intrinsics. Closes #89.
  • [Xtensa] Implement conditional move instrinsics. Closes #89.
  • [Xtensa] Add Boolean Extension feature. Closes #89.
  • [Xtensa] Add definition of S3 output registers. Xtensa S3 DSP instructions are coded using explicit register allocation. However, some instructions miss RegState:Define flag for output registers. This leads MachineVerifier to raise errors.

Bug Fixes:

  • [Toolchain][Espressif] Use custom prefixes for 'as' and 'ld'. To avoid conflicts with 'as' and 'ld' installed as part of IDF GCC-based toolchains. These tools will be replaced with integrated assembler and LLD in future.
  • [LLVM][Xtensa] Remove DFP accelrator feature from ESP32-S3.
  • [Xtensa] Fix disassembler. Fix disassembling of the Imm8_sh8, Imm64n_4n, Offset8m32, Entry_Imm12 immedaite operands.
  • [Clang] Fix undefined std::errc::state_not_recoverable for MinGW build. Replaced with std::errc::not_supported error code.
Assets 15
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